公开(公告)号：US20140159048A1

公开(公告)日：2014-06-12

申请号：US13898374

申请日：2013-05-20

申请人： Chih-Fang Huang ,  Po-Chin Peng ,  Tsung-Chieh Hsiao ,  Ya-Hsien Liu ,  K.C. Chang ,  Hung-Der Su ,  Chien-Wei Chiu ,  Tsung-Yi Huang ,  Tsung-Yu Yang ,  Ting-Fu Chang

发明人： Chih-Fang Huang ,  Po-Chin Peng ,  Tsung-Chieh Hsiao ,  Ya-Hsien Liu ,  K.C. Chang ,  Hung-Der Su ,  Chien-Wei Chiu ,  Tsung-Yi Huang ,  Tsung-Yu Yang ,  Ting-Fu Chang

IPC分类号： H01L29/778

CPC分类号： H01L29/66462 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/66431 ,  H01L29/7789

摘要： The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT device includes: a substrate, a first gallium nitride (GaN) layer; a P-type GaN layer, a second GaN layer, a barrier layer, a gate, a source, and a drain. The first GaN layer is formed on the substrate, and has a stepped contour from a cross-section view. The P-type GaN layer is formed on an upper step surface of the stepped contour, and has a vertical sidewall. The second GaN layer is formed on the P-type GaN layer. The barrier layer is formed on the second GaN layer. two dimensional electron gas regions are formed at junctions between the barrier layer and the first and second GaN layers. The gate is formed on an outer side of the vertical sidewall.

摘要翻译： 本发明公开了一种高电子迁移率晶体管（HEMT）及其制造方法。 HEMT器件包括：衬底，第一氮化镓（GaN）层; P型GaN层，第二GaN层，势垒层，栅极，源极和漏极。 第一GaN层形成在基板上，并且具有从横截面视图的阶梯状轮廓。 P型GaN层形成在阶梯状轮廓的上台阶面上，具有垂直侧壁。 第二GaN层形成在P型GaN层上。 阻挡层形成在第二GaN层上。 在阻挡层与第一和第二GaN层之间的接合处形成二维电子气体区域。 门形成在垂直侧壁的外侧。

公开(公告)号：US20140117443A1

公开(公告)日：2014-05-01

申请号：US14146512

申请日：2014-01-02

申请人： Ching-Yao Yang ,  Tsung-Yi Huang ,  Huan-Ping Chu ,  Hung-Der Su

发明人： Ching-Yao Yang ,  Tsung-Yi Huang ,  Huan-Ping Chu ,  Hung-Der Su

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78

CPC分类号： H01L29/4238 ,  H01L21/28114 ,  H01L21/823425 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.

公开(公告)号：US07838900B2

公开(公告)日：2010-11-23

申请号：US12385718

申请日：2009-04-17

申请人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

发明人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

IPC分类号： H01L29/74 ,  H01L31/111

CPC分类号： H01L27/098 ,  H01L27/0744 ,  H01L29/7722 ,  H01L29/8083

摘要： A single-chip common-drain JFET device comprises a Drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

摘要翻译： 单芯片公共漏极JFET器件包括漏极，两个栅极和两个源极，使得与其形成两个公共漏极JFET。 由于在单个芯片内合并的两个JFET，其间不需要引线接合连接，因此没有由接合线引起的寄生电感和电阻，因此提高性能并降低封装成本。 单片式公共漏极JFET器件可以应用于降压转换器，升压转换器，反相转换器，开关和两级DC-DC转换器，以提高其性能和效率。 还提供了用于电流感测或比例电流产生的替代单芯片公共漏极JFET器件。

公开(公告)号：US07728529B2

公开(公告)日：2010-06-01

申请号：US11149292

申请日：2005-06-10

申请人： Jing-Meng Liu ,  Chung-Lung Pai ,  Hung-Der Su

发明人： Jing-Meng Liu ,  Chung-Lung Pai ,  Hung-Der Su

IPC分类号： H05B37/02

CPC分类号： H05B33/0857 ,  H05B33/0818 ,  H05B33/0827 ,  Y02B20/347

摘要： In a LED driver using a depletion mode transistor to serve as a current source, the depletion mode transistor is self-biased for providing a driving current to drive at least one LED, thereby requesting no additional control circuit to control the depletion mode transistor. The driving current is independent on the supply voltage coupled to the at least one LED, thereby requesting no additional voltage regulator, reducing the circuit size, and lowering the cost.

摘要翻译： 在使用耗尽型晶体管作为电流源的LED驱动器中，耗尽型晶体管是自偏置的，用于提供驱动电流以驱动至少一个LED，从而不需要额外的控制电路来控制耗尽型晶体管。 驱动电流独立于耦合到至少一个LED的电源电压，从而不需要额外的电压调节器，减小电路尺寸并降低成本。

公开(公告)号：US07652536B2

公开(公告)日：2010-01-26

申请号：US12068774

申请日：2008-02-12

申请人： Hung-Der Su ,  Jing-Meng Liu ,  An-Tung Chen ,  Pao-Chuan Lin

发明人： Hung-Der Su ,  Jing-Meng Liu ,  An-Tung Chen ,  Pao-Chuan Lin

IPC分类号： H03F3/45 ,  H03F1/14

CPC分类号： H03F1/26 ,  H03F1/083 ,  H03F3/45197 ,  H03F2203/45356

摘要： An amplifier circuit with internal zeros provides a second pole in addition to a first pole and two zeros such that the second pole can prevent excessive gain at high frequency, so as to have high-frequency noise under control.

摘要翻译： 具有内部零点的放大器电路除了第一极点和第二极点之外还提供第二极点，使得第二极点可以在高频下防止过高的增益，从而具有控制的高频噪声。

公开(公告)号：US20090201079A1

公开(公告)日：2009-08-13

申请号：US12385720

申请日：2009-04-17

申请人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

发明人： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

IPC分类号： G05F3/02

CPC分类号： H01L27/098 ,  H01L27/0744 ,  H01L29/7722 ,  H01L29/8083

摘要： A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

公开(公告)号：US07557553B2

公开(公告)日：2009-07-07

申请号：US11650525

申请日：2007-01-08

申请人： Hung-Der Su ,  Jing-Meng Liu

发明人： Hung-Der Su ,  Jing-Meng Liu

IPC分类号： H03K19/0175

CPC分类号： H02M3/156

摘要： A power supply circuit and a control method are provided, in which the original enable pad and output pad, or the enable pad and feedback pad are used to trim the output voltage of the power supply circuit without extra trim pads.

摘要翻译： 提供了电源电路和控制方法，其中原始使能焊盘和输出焊盘或使能焊盘和反馈焊盘用于修剪电源电路的输出电压而无需额外的修整焊盘。

公开(公告)号：US20080018177A1

公开(公告)日：2008-01-24

申请号：US11826449

申请日：2007-07-16

申请人： Hung-Der Su ,  Jing-Meng Liu

发明人： Hung-Der Su ,  Jing-Meng Liu

IPC分类号： H01H83/00

CPC分类号： H02M1/08 ,  H02M3/156 ,  Y10T307/858

摘要： Two step driving technique is used to turn on the power switch of a power management apparatus in such a manner that the power switch is weakly turned on first and then goes into a low ON-resistance region. The power switch is so avoided to operate at highest gate and drain voltages simultaneously even a non-uniform turn on happens, and is thereby away from avalanche breakdown. The safe operation region of the power management apparatus is therefore extended with minimum efficiency degradation.

摘要翻译： 使用两步驱动技术，以使得电源开关首先弱开然后进入低导通电阻区域的方式来接通电源管理装置的电源开关。 电源开关如此避免同时在最高的栅极和漏极电压下工作，即使发生不均匀的导通，也因此远离雪崩击穿。 因此，功率管理装置的安全操作区域以最小的效率降低而延长。

公开(公告)号：US07132717B2

公开(公告)日：2006-11-07

申请号：US11109772

申请日：2005-04-20

申请人： Hung-Der Su ,  Chun-Yen Huang ,  Chung-Lung Pai ,  Jing-Meng Liu

发明人： Hung-Der Su ,  Chun-Yen Huang ,  Chung-Lung Pai ,  Jing-Meng Liu

IPC分类号： H01L29/94

CPC分类号： H01L29/41758 ,  H01L23/4824 ,  H01L29/4238 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A power metal oxide semiconductor transistor layout is disclosed. The power metal oxide semiconductor transistor layout uses network of conductive lead line as a connection or a network connection to connect source and drain regions thereby achieves advantages of a high uniformity of current, low Rds_on, much less power loss, an actual line density two times larger than that of conventional layouts and a strengthened resistance to electron migration.

摘要翻译： 公开了功率金属氧化物半导体晶体管布局。 功率金属氧化物半导体晶体管布局使用导电引线的网络作为连接或网络连接来连接源极和漏极区域，从而实现电流高均匀性，低Rds_on，更少功率损耗，实际线密度两倍的优点 大于常规布局，并且具有增强的电子迁移性。

公开(公告)号：US20060138565A1

公开(公告)日：2006-06-29

申请号：US11109772

申请日：2005-04-20

申请人： Hung-Der Su ,  Chun-Yen Huang ,  Chung-Lung Pai ,  Jing-Meng Liu

发明人： Hung-Der Su ,  Chun-Yen Huang ,  Chung-Lung Pai ,  Jing-Meng Liu

IPC分类号： H01L29/76

CPC分类号： H01L29/41758 ,  H01L23/4824 ,  H01L29/4238 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A power metal oxide semiconductor transistor layout is disclosed. The power metal oxide semiconductor transistor layout uses network of conductive lead line as a connection or a network connection to connect source and drain regions thereby achieves advantages of a high uniformity of current, low Rds_on, much less power loss, an actual line density two times larger than that of conventional layouts and a strengthened resistance to electron migration.