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121 条记录 (耗时 0.037 秒)

    Multi-layer memory devices
    61.
    发明授权
    Multi-layer memory devices 有权
    多层存储设备

    公开(公告)号：US08258563B2

    公开(公告)日：2012-09-04

    申请号：US13049495

    申请日：2011-03-16

    申请人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    发明人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    IPC分类号： H01L29/76

    CPC分类号： H01L27/105 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

    摘要： A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.

    摘要翻译： 非易失性存储器件包括具有第一导电类型的第一阱区和形成在半导体衬底上的至少一个半导体层的半导体衬底。 第一单元阵列形成在半导体衬底上，第二单元阵列形成在半导体层上。 半导体层包括第一导电类型的第二阱区，其具有大于第一导电类型的第一阱区的掺杂浓度的掺杂浓度。 随着第二阱区域的掺杂浓度增加，可以在第一和第二阱区域之间减小电阻差。

    Node contact structures in semiconductor devices
    63.
    发明授权
    Node contact structures in semiconductor devices 有权
    半导体器件中的节点接触结构

    公开(公告)号：US07521715B2

    公开(公告)日：2009-04-21

    申请号：US11032725

    申请日：2005-01-11

    申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

    发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

    IPC分类号： H01L27/108

    CPC分类号： H01L27/11 ,  H01L27/1108 ,  Y10S257/903

    摘要： A static random-access memory (SRAM) device may include a bulk MOS transistor on a semiconductor substrate having a source/drain region therein, an insulating layer on the bulk MOS transistor, and a thin-film transistor having a source/drain region therein on the insulating layer above the bulk MOS transistor. The device may further include a multi-layer plug between the bulk MOS transistor and the thin-film transistor. The multi-layer plug may include a semiconductor plug directly on the source/drain region of the bulk MOS transistor and extending through at least a portion of the insulating layer, and a metal plug directly on the source/drain region of the thin-film transistor and the semiconductor plug and extending through at least a portion of the insulating layer. Related methods are also discussed.

    摘要翻译： 静态随机存取存储器（SRAM）器件可以包括在其中具有源极/漏极区域的半导体衬底上的体MOS晶体管，体MOS晶体管上的绝缘层，以及在其中具有源极/漏极区域的薄膜晶体管 在体MOS晶体管上方的绝缘层上。 器件还可以包括在体MOS晶体管和薄膜晶体管之间的多层插头。 多层插头可以包括直接在体MOS晶体管的源极/漏极区域上并延伸穿过绝缘层的至少一部分的半导体插头，以及直接在薄膜的源极/漏极区域上的金属插塞 晶体管和半导体插头并延伸穿过绝缘层的至少一部分。 还讨论了相关方法。

    Methods of fabricating a semiconductor device having a node contact structure of a CMOS inverter
    64.
    发明授权
    Methods of fabricating a semiconductor device having a node contact structure of a CMOS inverter 有权
    制造具有CMOS反相器的节点接触结构的半导体器件的方法

    公开(公告)号：US07387919B2

    公开(公告)日：2008-06-17

    申请号：US11281346

    申请日：2005-11-16

    申请人： Kun-Ho Kwak ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Jong-Hyuk Kim

    发明人： Kun-Ho Kwak ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Jong-Hyuk Kim

    IPC分类号： H01L21/00 ,  H01L21/84

    CPC分类号： H01L21/8221 ,  H01L27/0688 ,  H01L27/092

    摘要： In one embodiment, an intrinsic single crystalline semiconductor plug is formed to pass through a lower insulating layer using a selective epitaxial growth process employing a node impurity region as a seed layer, and a single crystalline semiconductor body pattern is formed on the lower insulating layer using the intrinsic single crystalline semiconductor plug as a seed layer. When the recessed single crystalline semiconductor plug is doped with impurities having the same conductivity type as the node impurity region, a peripheral impurity region is prevented from being counter-doped. As a result, it is possible to implement a high performance semiconductor device that requires a single crystalline thin film transistor as well as a node contact structure with ohmic contact.

    摘要翻译： 在一个实施例中，使用使用节点杂质区域作为种子层的选择性外延生长工艺，形成本征单晶半导体插塞以穿过下绝缘层，并且在下绝缘层上形成单晶体半导体本体图案，使用 本征单晶半导体插头作为种子层。 当嵌入的单晶半导体插件掺杂有与节点杂质区相同的导电类型的杂质时，防止外围杂质区域被反掺杂。 结果，可以实现需要单晶薄膜晶体管的高性能半导体器件以及具有欧姆接触的节点接触结构。

    Multi-layer nonvolatile memory devices and methods of fabricating the same
    65.
    发明申请
    Multi-layer nonvolatile memory devices and methods of fabricating the same 审中-公开
    多层非易失性存储器件及其制造方法

    公开(公告)号：US20080108213A1

    公开(公告)日：2008-05-08

    申请号：US11654133

    申请日：2007-01-17

    申请人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    发明人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    IPC分类号： H01L21/4763 ,  H01L21/3205

    CPC分类号： H01L27/105 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

    摘要： A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.

    摘要翻译： 非易失性存储器件包括具有第一导电类型的第一阱区和形成在半导体衬底上的至少一个半导体层的半导体衬底。 第一单元阵列形成在半导体衬底上，第二单元阵列形成在半导体层上。 半导体层包括第一导电类型的第二阱区，其具有大于第一导电类型的第一阱区的掺杂浓度的掺杂浓度。 随着第二阱区域的掺杂浓度增加，可以在第一和第二阱区域之间减小电阻差。

    Methods of fabricating semiconductor devices having thin film transistors
    68.
    发明授权
    Methods of fabricating semiconductor devices having thin film transistors 有权
    制造具有薄膜晶体管的半导体器件的方法

    公开(公告)号：US07312110B2

    公开(公告)日：2007-12-25

    申请号：US11098648

    申请日：2005-04-04

    申请人： Kun-Ho Kwak ,  Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Hoon Lim ,  Jong-Hyuk Kim ,  Myang-Sik Han ,  Byung-Jun Hwang

    发明人： Kun-Ho Kwak ,  Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Hoon Lim ,  Jong-Hyuk Kim ,  Myang-Sik Han ,  Byung-Jun Hwang

    IPC分类号： H01L21/00

    CPC分类号： H01L27/1108 ,  H01L27/0688 ,  H01L27/11 ,  H01L29/78603

    摘要： Methods of fabricating semiconductor devices are provided. An interlayer insulating layer is provided on a single crystalline semiconductor substrate. A single crystalline semiconductor plug is provided that extends through the interlayer insulating layer and a molding layer pattern is provided on the semiconductor substrate and the single crystalline semiconductor plug. The molding layer pattern defines an opening therein that at least partially exposes a portion of the single crystalline semiconductor plug. A single crystalline semiconductor epitaxial pattern is provided on the exposed portion of single crystalline semiconductor plug using a selective epitaxial growth technique that uses the exposed portion of the single crystalline semiconductor plug as a seed layer. A single crystalline semiconductor region is provided in the opening. The single crystalline semiconductor region includes at least a portion of the single crystalline semiconductor epitaxial pattern.

    摘要翻译： 提供制造半导体器件的方法。 层间绝缘层设置在单晶半导体衬底上。 提供延伸穿过层间绝缘层的单晶半导体插头，并且在半导体衬底和单晶半导体插头上设置成型层图案。 模制层图案限定其中的开口，其至少部分地暴露单晶半导体插塞的一部分。 使用选择性外延生长技术在单晶半导体插塞的暴露部分上提供单晶半导体外延图案，其使用单晶半导体插塞的暴露部分作为籽晶层。 在开口中设置单晶半导体区域。 单晶半导体区域包括单晶半导体外延图案的至少一部分。

    Methods of forming SRAM cells having landing pad in contact with upper and lower cell gate patterns
    69.
    发明申请
    Methods of forming SRAM cells having landing pad in contact with upper and lower cell gate patterns 有权
    形成具有与上和下单元栅极图案接触的着陆焊盘的SRAM单元的方法

    公开(公告)号：US20070042554A1

    公开(公告)日：2007-02-22

    申请号：US11589618

    申请日：2006-10-30

    申请人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Jong-Hyuk Kim ,  Jae-Joo Shim

    发明人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Jong-Hyuk Kim ,  Jae-Joo Shim

    IPC分类号： H01L21/336

    CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1108 ,  Y10S257/903

    摘要： SRAM cells having landing pads in contact with upper and lower cell gate patterns, and methods of forming the same are provided. The SRAM cells and the methods remove the influence resulting from structural characteristics of the SRAM cells having vertically stacked upper and lower gate patterns, for stably connecting the patterns on the overall surface of the semiconductor substrate. An isolation layer isolating at least one lower active region is formed in a semiconductor substrate of the cell array region. The lower active region has two lower cell gate patterns. A body pattern is disposed in parallel with the semiconductor substrate. The body pattern is formed to confine an upper active region, which has upper cell gate patterns on the lower cell gate patterns. A landing pad is disposed between the lower cell gate patterns. A node pattern is formed to simultaneously contact the upper cell gate pattern and the lower cell gate pattern.

    摘要翻译： 提供了具有与上下单元栅极图案接触的接合焊盘的SRAM单元及其形成方法。 SRAM单元和方法消除了由于具有垂直堆叠的上下栅极图案的SRAM单元的结构特性而产生的影响，用于稳定地连接半导体衬底的整个表面上的图案。 在电池阵列区域的半导体衬底中形成隔离至少一个下部有源区的隔离层。 下部有源区域具有两个较低的单元栅极图案。 主体图案与半导体衬底平行设置。 形成主体图形以限制在下单元门图案上具有上单元栅极图案的上有源区。 着陆垫设置在下单元栅极图案之间。 形成节点图案以同时接触上单元格栅图案和下单元栅格图案。