公开(公告)号：US08076712B2

公开(公告)日：2011-12-13

申请号：US12840165

申请日：2010-07-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

IPC分类号： H01L29/788

CPC分类号： H01L29/42332 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/7887 ,  H01L29/7923

摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

摘要翻译： 提供了双电荷存储节点存储器件及其制造方法。 在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。 在第二部分上形成一层半导体材料。 第一层状结构形成在电介质塞的第二部分的第一侧上，并且第二层结构形成在第二侧上，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层 和第二电介质层。 将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

公开(公告)号：US07911238B2

公开(公告)日：2011-03-22

申请号：US10958364

申请日：2004-10-06

申请人： Michael Lin ,  Chi Chang

发明人： Michael Lin ,  Chi Chang

IPC分类号： G06F1/08

CPC分类号： G06F1/08 ,  H03K17/005

摘要： A switch circuit for switching two clock signals includes a clock generator, a flip-flop and a multiplexer. The clock generator is to generate a reference signal whose cycle is the lowest common multiple of the cycles of the two clock signals. The flip-flop is to generate a selecting signal by taking a control signal from system as an input signal and taking the reference signal as a timing trigger signal. The multiplexer can output a selected clock signal according to the selecting signal in which the selected clock signal and the switched clock signal are synchronous during their entire cycles.

摘要翻译： 用于切换两个时钟信号的开关电路包括时钟发生器，触发器和多路复用器。 时钟发生器产生一个参考信号，其周期是两个时钟信号周期的最低公倍数。 触发器通过从系统的控制信号作为输入信号并且将参考信号作为定时触发信号来产生选择信号。 多路复用器可以根据所选择的时钟信号和开关时钟信号在其整个周期期间是同步的选择信号输出所选择的时钟信号。

公开(公告)号：US07767517B2

公开(公告)日：2010-08-03

申请号：US11613513

申请日：2006-12-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

IPC分类号： H01L21/8242

CPC分类号： H01L29/42332 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/7887 ,  H01L29/7923

摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

摘要翻译： 提供了双电荷存储节点存储器件及其制造方法。 在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。 在第二部分上形成一层半导体材料。 第一层状结构形成在电介质塞的第二部分的第一侧上，并且形成在第二侧上的第二层状结构，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层 和第二电介质层。 将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

公开(公告)号：US07733129B2

公开(公告)日：2010-06-08

申请号：US12167797

申请日：2008-07-03

申请人： Chi Chang

发明人： Chi Chang

IPC分类号： H03K19/00

CPC分类号： G06F1/04

摘要： A memory clock signal is generated in response to a reference clock signal and a clock enable signal. The memory clock signal with a frequency identical to that of the reference clock signal is generated during the clock enable signal is in an enabled state; and the memory clock signal with a reduced frequency is generated when the clock enable signal is changed from the enabled state to a disabled state. The generation of a memory clock signal is adaptive so as to save power.

摘要翻译： 响应于参考时钟信号和时钟使能信号产生存储器时钟信号。 在时钟使能信号处于使能状态时产生具有与参考时钟信号的频率相同频率的存储器时钟信号; 并且当时钟使能信号从使能状态改变为禁止状态时，产生频率降低的存储器时钟信号。 存储器时钟信号的产生是自适应的，以便节省功率。

公开(公告)号：US07721137B2

公开(公告)日：2010-05-18

申请号：US11513198

申请日：2006-08-31

申请人： Ming-Te Lin ,  Chi Chang

发明人： Ming-Te Lin ,  Chi Chang

IPC分类号： H03K4/06

CPC分类号： G06F13/4072

摘要： A bus receiver receives at least one first signal and a second signal both generated from a chip connected to a parallel bus. The bus receiver includes a receiving module and a deskewing module. The receiving module is electrically connected to the parallel bus and receives the first signal and the second signal transmitted through the parallel bus. The deskewing module is electrically connected to the receiving module and deskews the phase of the first signal and the phase of the second signal. The first signal and the second signal are in the same phase.

摘要翻译： 总线接收器接收从连接到并行总线的芯片产生的至少一个第一信号和第二信号。 总线接收器包括接收模块和偏移模块。 接收模块电连接到并行总线，并接收通过并行总线传输的第一信号和第二信号。 歪斜模块电连接到接收模块，并且对第一信号的相位和第二信号的相位进行歪斜。 第一信号和第二信号处于相同的相位。

公开(公告)号：US20080149999A1

公开(公告)日：2008-06-26

申请号：US11613513

申请日：2006-12-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/42332 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/7887 ,  H01L29/7923

摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

摘要翻译： 提供了双电荷存储节点存储器件及其制造方法。 在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。 在第二部分上形成一层半导体材料。 第一层状结构形成在电介质塞的第二部分的第一侧上，并且形成在第二侧上的第二层状结构，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层 和第二电介质层。 将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

公开(公告)号：US20080061359A1

公开(公告)日：2008-03-13

申请号：US11702847

申请日：2007-02-05

申请人： Chungho Lee ,  Hiroyuki Kinoshita ,  Zoran Krivokapic ,  Wei Zheng ,  Mark Chang ,  Rinji Sugino ,  Chi Chang

发明人： Chungho Lee ,  Hiroyuki Kinoshita ,  Zoran Krivokapic ,  Wei Zheng ,  Mark Chang ,  Rinji Sugino ,  Chi Chang

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7885 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

摘要： An embodiment of the present invention is directed to a memory cell. The memory cell includes a stack formed over a substrate. The stack includes a gate oxide layer and an overlying polycrystalline silicon layer. The stack further includes first and second undercut regions formed under the polycrystalline silicon layer and adjacent to the gate oxide layer. The memory cell further includes a first charge storage element formed in the first undercut region and a second charge storage element formed in the second undercut region.

摘要翻译： 本发明的实施例涉及存储单元。 存储单元包括形成在衬底上的堆叠。 堆叠包括栅极氧化物层和上覆的多晶硅层。 堆叠还包括形成在多晶硅层下方并与栅极氧化物层相邻的第一和第二底切区域。 存储单元还包括形成在第一底切区域中的第一电荷存储元件和形成在第二底切区域中的第二电荷存储元件。

公开(公告)号：US20080052493A1

公开(公告)日：2008-02-28

申请号：US11758772

申请日：2007-06-06

申请人： Chi Chang

发明人： Chi Chang

IPC分类号： G06F15/00

CPC分类号： G06F1/3203 ,  G06F1/3293 ,  G06F9/30189 ,  G06F9/3885 ,  Y02D10/122

摘要： A processor for a portable electronic device. The processor includes a RISC (reduced instruction set computing) core a CISC (complex instruction set computing) core, a video accelerator circuit and an audio accelerator circuit. Each of the video and audio accelerator circuits are coupled to both the RISC and CISC cores, with both cores and both accelerator circuit being incorporated into a single integrated circuit. In a first plurality of operational modes, the RISC core is active, while the CISC core is in one of a sleep state or a power off state. In a second plurality of modes, both the RISC and CISC cores are active.

摘要翻译： 一种用于便携式电子设备的处理器。 该处理器包括RISC（精简指令集计算）核心，CISC（复杂指令集计算）核心，视频加速器电路和音频加速器电路。 每个视频和音频加速器电路都耦合到RISC和CISC核心，两个核心和两个加速器电路都被并入单个集成电路中。 在第一多个操作模式中，RISC核心是活动的，而CISC核心处于休眠状态或断电状态之一。 在第二种多种模式中，RISC和CISC内核都是活动的。

公开(公告)号：US20080044000A1

公开(公告)日：2008-02-21

申请号：US11756797

申请日：2007-06-01

申请人： Chi Chang

发明人： Chi Chang

IPC分类号： H04M1/00

CPC分类号： H04M1/2473 ,  G06F3/021 ,  G06F3/023 ,  G06F3/0489

摘要： A computer system including telephone functionality. The computer system includes a first keyboard and a first display. The computer system also includes a processor having at least a first functional unit and a second functional unit, and further includes a phone portion. The computer system may operate in a first mode, a second mode, or a third mode. In the first mode, only the phone portion is activated. In the second mode, the phone portion and first functional unit of the processor are activated. In the third mode, each of the phone portion, the first functional unit, and the second functional unit are activated.

摘要翻译： 包括电话功能的计算机系统。 计算机系统包括第一键盘和第一显示器。 计算机系统还包括具有至少第一功能单元和第二功能单元的处理器，并且还包括电话部分。 计算机系统可以在第一模式，第二模式或第三模式中操作。 在第一模式中，只有手机部分被激活。 在第二模式中，处理器的电话部分和第一功能单元被激活。 在第三模式中，电话部分，第一功能单元和第二功能单元中的每一个被激活。

公开(公告)号：US07313187B2

公开(公告)日：2007-12-25

申请号：US10856044

申请日：2004-05-28

申请人： Chi Chang

发明人： Chi Chang

IPC分类号： H04B3/00 ,  H04L25/06

CPC分类号： H04L25/0288 ,  H04L25/0272

摘要： A high-speed serial linking device with de-emphasis function for receiving a parallel data and accordingly outputting a de-emphasized transmission differential pair. The high-speed serial linking device includes a parallel-to-serial unit, a pre-driver, and an output driver. The parallel-to-serial unit is used to receive a parallel data and further serializes the parallel data into a serial data and a delayed serial data. The pre-driver outputs a data differential pair according to the serial data and outputs a delayed-and-inverted differential pair according to the delayed serial data. The output driver unit is used to receive the data differential pair and the delayed-and-inverted differential pair to accordingly output a de-emphasized transmission differential pair.

摘要翻译： 一种具有去加重功能的高速串行连接装置，用于接收并行数据，并相应地输出去强调的传输差分对。 高速串行连接装置包括并行到串行单元，预驱动器和输出驱动器。 并行到串行单元用于接收并行数据，并将并行数据串行化为串行数据和延迟串行数据。 预驱动器根据串行数据输出数据差分对，并根据延迟的串行数据输出延迟和反相差分对。 输出驱动器单元用于接收数据差分对和延迟和反相差分对，从而相应地输出去强调的传输差分对。