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    Bus receiver and method of deskewing bus signals
    1.
    发明申请
    Bus receiver and method of deskewing bus signals 有权
    总线接收器和校正总线信号的校正方法

    公开(公告)号：US20070074061A1

    公开(公告)日：2007-03-29

    申请号：US11513198

    申请日：2006-08-31

    申请人： Ming-Te Lin ,  Chi Chang

    发明人： Ming-Te Lin ,  Chi Chang

    IPC分类号： G06F1/00

    CPC分类号： G06F13/4072

    摘要： A bus receiver receives at least one first signal and a second signal both generated from a chip connected to a parallel bus. The bus receiver includes a receiving module and a deskewing module. The receiving module is electrically connected to the parallel bus and receives the first signal and the second signal transmitted through the parallel bus. The deskewing module is electrically connected to the receiving module and deskews the phase of the first signal and the phase of the second signal. The first signal and the second signal are in the same phase.

    摘要翻译： 总线接收器接收从连接到并行总线的芯片产生的至少一个第一信号和第二信号。 总线接收器包括接收模块和偏移模块。 接收模块电连接到并行总线，并接收通过并行总线传输的第一信号和第二信号。 歪斜模块电连接到接收模块，并且对第一信号的相位和第二信号的相位进行歪斜。 第一信号和第二信号处于相同的相位。

    Bus receiver and method of deskewing bus signals
    2.
    发明授权
    Bus receiver and method of deskewing bus signals 有权
    总线接收器和校正总线信号的校正方法

    公开(公告)号：US07721137B2

    公开(公告)日：2010-05-18

    申请号：US11513198

    申请日：2006-08-31

    申请人： Ming-Te Lin ,  Chi Chang

    发明人： Ming-Te Lin ,  Chi Chang

    IPC分类号： H03K4/06

    CPC分类号： G06F13/4072

    摘要： A bus receiver receives at least one first signal and a second signal both generated from a chip connected to a parallel bus. The bus receiver includes a receiving module and a deskewing module. The receiving module is electrically connected to the parallel bus and receives the first signal and the second signal transmitted through the parallel bus. The deskewing module is electrically connected to the receiving module and deskews the phase of the first signal and the phase of the second signal. The first signal and the second signal are in the same phase.

    摘要翻译： 总线接收器接收从连接到并行总线的芯片产生的至少一个第一信号和第二信号。 总线接收器包括接收模块和偏移模块。 接收模块电连接到并行总线，并接收通过并行总线传输的第一信号和第二信号。 歪斜模块电连接到接收模块，并且对第一信号的相位和第二信号的相位进行歪斜。 第一信号和第二信号处于相同的相位。

    Computer system and processor having integrated phone functionality
    3.
    发明授权
    Computer system and processor having integrated phone functionality 有权
    具有集成手机功能的计算机系统和处理器

    公开(公告)号：US09106734B2

    公开(公告)日：2015-08-11

    申请号：US13584527

    申请日：2012-08-13

    申请人： Chi Chang

    发明人： Chi Chang

    IPC分类号： H04M11/00 ,  H04M1/247 ,  G06F3/02 ,  G06F3/023 ,  G06F3/0489

    CPC分类号： H04M1/2473 ,  G06F3/021 ,  G06F3/023 ,  G06F3/0489

    摘要： A computer system including telephone functionality. The computer system includes a first keyboard and a first display. The computer system also includes a processor having at least a first functional unit and a second functional unit, and further includes a phone portion. The computer system may operate in a first mode, a second mode, or a third mode. In the first mode, only the phone portion is activated, and the phone portion provides a functionality of placing and receiving phone calls without being removed from the computer system. In the second mode, the phone portion and first functional unit of the processor are activated. In the third mode, each of the phone portion, the first functional unit, and the second functional unit are activated.

    摘要翻译： 包括电话功能的计算机系统。 计算机系统包括第一键盘和第一显示器。 计算机系统还包括具有至少第一功能单元和第二功能单元的处理器，并且还包括电话部分。 计算机系统可以在第一模式，第二模式或第三模式中操作。 在第一模式中，只有电话部分被激活，并且电话部分提供放置和接收电话呼叫的功能，而不从计算机系统移除。 在第二模式中，处理器的电话部分和第一功能单元被激活。 在第三模式中，电话部分，第一功能单元和第二功能单元中的每一个被激活。

    Dual charge storage node memory device and methods for fabricating such device
    5.
    发明授权
    Dual charge storage node memory device and methods for fabricating such device 有权
    双电荷存储节点存储器件及其制造方法

    公开(公告)号：US07915123B1

    公开(公告)日：2011-03-29

    申请号：US11408866

    申请日：2006-04-20

    申请人： Chungho Lee ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Kyunghoon Min ,  Chi Chang

    发明人： Chungho Lee ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Kyunghoon Min ,  Chi Chang

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7883 ,  H01L29/792 ,  Y10S438/954

    摘要： A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers.

    摘要翻译： 提供了一种双节点存储器件及其制造方法。 在一个实施例中，该方法包括在半导体衬底上形成具有绝缘体层，电荷存储层，缓冲层和牺牲层的分层结构。 这些层被图案化以形成两个间隔开的堆叠和在堆叠之间的暴露的衬底部分。 在暴露的基板上形成栅极绝缘体和栅电极，去除牺牲层和缓冲层。 沉积覆盖电荷存储层的另外的绝缘体层，以在栅电极的每一侧上形成绝缘体存储层 - 绝缘体存储器存储区域。 侧壁间隔件形成在覆盖存储区域的栅电极的侧壁上。 在与栅极间隔开的衬底中形成位线，并且形成与栅电极和侧壁间隔物接触的字线。

    P-channel NAND in isolated N-well
    6.
    发明授权
    P-channel NAND in isolated N-well 有权
    隔离N阱中的P沟道NAND

    公开(公告)号：US07671403B2

    公开(公告)日：2010-03-02

    申请号：US11567257

    申请日：2006-12-06

    申请人： Wei Zheng ,  Chi Chang ,  Mark Randolph ,  Satoshi Torii

    发明人： Wei Zheng ,  Chi Chang ,  Mark Randolph ,  Satoshi Torii

    IPC分类号： H01L29/792

    CPC分类号： H01L27/115 ,  H01L27/11568

    摘要： A device includes a substrate and multiple wells formed over the substrate and isolated from one another by dielectric trenches. The device further includes multiple memory elements formed over the wells, each of the memory elements extending approximately perpendicular to the wells and including a material doped with n-type impurities. The device also includes multiple source/drain regions, each source/drain region formed within one of multiple trenches and inside one of the plurality of wells between a pair of the memory elements, each of the source/drain regions implanted with p-type impurities. The device further includes a first substrate contact formed in a first one of the multiple trenches through a first one of the wells into the substrate and a second substrate contact formed in a second one of the multiple trenches through a second one of the wells into the substrate.

    摘要翻译： 一种器件包括衬底和形成在衬底上并由电介质沟槽彼此隔离的多个阱。 该器件还包括形成在阱上的多个存储元件，每个存储元件大致垂直于阱延伸并且包括掺杂有n型杂质的材料。 器件还包括多个源极/漏极区域，每个源极/漏极区域形成在多个沟槽中的一个内，并且在一对存储元件之间的多个阱中的一个内部，源极/漏极区域中的每一个注入p型杂质 。 所述器件还包括形成在所述多个沟槽中的第一个沟槽中的第一衬底接触件，穿过所述衬底中的第一孔，以及形成在所述多个沟槽中的第二个沟槽中的第二衬底接触件中的第二衬底接触入第 基质。

    Method and circuitry for extracting clock in clock data recovery system
    7.
    发明授权
    Method and circuitry for extracting clock in clock data recovery system 有权
    在时钟数据恢复系统中提取时钟的方法和电路

    公开(公告)号：US07616722B2

    公开(公告)日：2009-11-10

    申请号：US11148852

    申请日：2005-06-08

    申请人： Chi Chang ,  Shuyu Lin

    发明人： Chi Chang ,  Shuyu Lin

    IPC分类号： H04L7/00

    CPC分类号： H04L7/02

    摘要： A method for extracting a clock in a clock data recovery system is provided. The method includes the following steps. First, a serial link transmission data is sampled for a plurality of times, and a plurality of pulse signals are generated and sequentially arranged. Then, a mark is inserted after all pulse signals are generated and had been delayed for a predetermined delay time. The predetermined delay time is less than a period between two adjacent pulse signals, and a period between two adjacent pulse signals is divided into two sub-periods by the predetermined delay time. Then, it is checked whether the data status in each sub-period is changed or not, and this operation is repeated for a predetermined number of times. Finally, the clock is extracted when a pulse signal of no data status change within the predetermined number of times is being generated.

    摘要翻译： 提供了一种在时钟数据恢复系统中提取时钟的方法。 该方法包括以下步骤。 首先，对多个串行链路发送数据进行采样，生成多个脉冲信号并依次排列。 然后，在产生所有脉冲信号之后插入一个标记，并将其延迟预定的延迟时间。 预定的延迟时间小于两个相邻脉冲信号之间的周期，并且两个相邻脉冲信号之间的周期被划分为两个子周期预定的延迟时间。 然后，检查每个子周期中的数据状态是否改变，并且该操作重复预定次数。 最后，当生成在预定次数内没有数据状态改变的脉冲信号时，提取时钟。

    Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes
    8.
    发明申请
    Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes 有权
    具有分离电荷存储节点的存储单元和用于制造具有分离电荷存储节点的存储单元的方法

    公开(公告)号：US20080142875A1

    公开(公告)日：2008-06-19

    申请号：US11639666

    申请日：2006-12-15

    申请人： Chungho Lee ,  Wei Zheng ,  Chi Chang ,  Unsoon Kim ,  Hiroyuki Kinoshita

    发明人： Chungho Lee ,  Wei Zheng ,  Chi Chang ,  Unsoon Kim ,  Hiroyuki Kinoshita

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/1037 ,  H01L29/1083 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66537 ,  H01L29/7887 ,  H01L29/7923

    摘要： Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes are disclosed. A disclosed method includes forming a first trench and an adjacent second trench in a semiconductor substrate, the first trench and the second trench each defining a first sidewall and a second sidewall respectively and forming a first source/drain region in the substrate and a second source/drain region in the substrate, where the first source/drain region and the second source/drain region are formed substantially under the first trench and the second trench in the semiconductor substrate respectively. Moreover, a method includes forming a bit line punch through barrier in the substrate between the first source/drain region and the second source drain region and forming a first storage element on the first sidewall of the first trench and a second storage element on the second sidewall of the second element. A word line is formed in contact with the first storage element and the second storage element.

    摘要翻译： 公开了具有分割电荷存储节点的存储单元和用于制造具有分离电荷存储节点的存储单元的方法。 所公开的方法包括在半导体衬底中形成第一沟槽和相邻的第二沟槽，第一沟槽和第二沟槽分别限定第一侧壁和第二侧壁，并在衬底中形成第一源极/漏极区域，第二源极 /漏极区域，其中第一源极/漏极区域和第二源极/漏极区域分别基本上形成在半导体衬底中的第一沟槽和第二沟槽下方。 此外，一种方法包括在第一源极/漏极区域和第二源极漏极区域之间的衬底中形成位线穿通阻挡层，并在第一沟槽的第一侧壁上形成第一存储元件，在第二沟槽的第二沟槽上形成第二存储元件 第二元件的侧壁。 形成与第一存储元件和第二存储元件接触的字线。

    P-CHANNEL NAND IN ISOLATED N-WELL
    9.
    发明申请
    P-CHANNEL NAND IN ISOLATED N-WELL 有权
    P-CHANNEL NAND在隔离N-WELL中

    公开(公告)号：US20080135918A1

    公开(公告)日：2008-06-12

    申请号：US11567257

    申请日：2006-12-06

    申请人： Wei Zheng ,  Chi Chang ,  Mark Randolph ,  Satoshi Torii

    发明人： Wei Zheng ,  Chi Chang ,  Mark Randolph ,  Satoshi Torii

    IPC分类号： H01L27/115

    CPC分类号： H01L27/115 ,  H01L27/11568

    摘要： A device includes a substrate and multiple wells formed over the substrate and isolated from one another by dielectric trenches. The device further includes multiple memory elements formed over the wells, each of the memory elements extending approximately perpendicular to the wells and including a material doped with n-type impurities. The device also includes multiple source/drain regions, each source/drain region formed within one of multiple trenches and inside one of the plurality of wells between a pair of the memory elements, each of the source/drain regions implanted with p-type impurities. The device further includes a first substrate contact formed in a first one of the multiple trenches through a first one of the wells into the substrate and a second substrate contact formed in a second one of the multiple trenches through a second one of the wells into the substrate.

    摘要翻译： 一种器件包括衬底和形成在衬底上并由电介质沟槽彼此隔离的多个阱。 该器件还包括形成在阱上的多个存储元件，每个存储元件大致垂直于阱延伸并且包括掺杂有n型杂质的材料。 器件还包括多个源极/漏极区域，每个源极/漏极区域形成在多个沟槽中的一个内，并且在一对存储元件之间的多个阱中的一个内部，源极/漏极区域中的每一个注入p型杂质 。 所述器件还包括形成在所述多个沟槽中的第一个沟槽中的第一衬底接触件，穿过所述衬底中的第一孔，以及形成在所述多个沟槽中的第二个沟槽中的第二衬底接触件中的第二衬底接触入第 基质。