公开(公告)号：US5634065A

公开(公告)日：1997-05-27

申请号：US475134

申请日：1995-06-07

申请人： Karl M. Guttag ,  Keith Balmer ,  Robert J. Gove ,  Christopher J. Read ,  Jeremiah E. Golston ,  Sydney W. Poland ,  Nicholas Ing-Simmons ,  Philip Moyse

发明人： Karl M. Guttag ,  Keith Balmer ,  Robert J. Gove ,  Christopher J. Read ,  Jeremiah E. Golston ,  Sydney W. Poland ,  Nicholas Ing-Simmons ,  Philip Moyse

IPC分类号： G06F5/01 ,  G06F7/575 ,  G06F7/76 ,  G06F7/38

CPC分类号： G06F7/764 ,  G06F5/01 ,  G06F7/575

摘要： A three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default barrel rotate amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register.

摘要翻译： 三输入算术逻辑单元（230），其生成由功能信号选择的三个输入的组合。 第二输入信号来自可控筒旋转器（235）。 旋转量是存储在特殊数据寄存器中的默认旋转量，从数据寄存器或零调用的预定数据位组。 恒定源（236）连接到筒旋转器（235）以提供“1”的多位数字信号。 这允许产生形式2N的第二输入信号，其中N是旋转量。 桶旋转器（235）的输出可以独立于算术逻辑单元（230）的结果存储。 第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。 掩模的一个优选形式具有对应于掩模输入信号的许多右对齐1。 该掩模输入信号可以是由多路复用器选择的默认桶旋转量或第三输入信号的预定数量的最低有效位。 选择掩模的第二优选形式是从数据寄存器回调的数据的最低有效位的预定集合的最左1，最右1，最左位变化或最右位变化中的一个。

公开(公告)号：US5600847A

公开(公告)日：1997-02-04

申请号：US475162

申请日：1995-06-07

申请人： Karl M. Guttag ,  Keith Balmer ,  Robert J. Gove ,  Christopher J. Read ,  Jeremiah E. Golston ,  Sydney W. Poland ,  Nicholas Ing-Simmons ,  Philip Moyse

发明人： Karl M. Guttag ,  Keith Balmer ,  Robert J. Gove ,  Christopher J. Read ,  Jeremiah E. Golston ,  Sydney W. Poland ,  Nicholas Ing-Simmons ,  Philip Moyse

IPC分类号： G06F7/57 ,  G06F7/38

CPC分类号： G06F7/57

摘要： A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. A controllable shifter is an alternative to the barrel rotator (235). The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default barrel rotate amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.

摘要翻译： 数据处理装置包括产生由功能信号选择的三个输入的组合的三输入算术逻辑单元（230）。 数据寄存器（200）存储三个数据输入和算术逻辑单元输出。 第二输入信号来自可控筒旋转器（235）。 旋转量是存储在特殊数据寄存器中的默认旋转量，从数据寄存器或零调用的预定数据位组。 恒定源（236）连接到筒旋转器（235）以提供“1”的多位数字信号。 这允许产生形式2N的第二输入信号，其中N是旋转量。 桶旋转器（235）的输出可以独立于算术逻辑单元（230）的结果存储。 可控制的换档器是桶旋转器（235）的替代品。 第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。 掩模的一个优选形式具有对应于掩模输入信号的许多右对齐1。 该掩模输入信号可以是由多路复用器选择的默认桶旋转量或第三输入信号的预定数量的最低有效位。 选择掩模的第二优选形式是从数据寄存器回调的数据的最低有效位的预定集合的最左1，最右1，最左位变化或最右位变化中的一个。 在本发明的优选实施例中，三输入算术逻辑单元（230）被实现为作为在图像处理中使用的多处理器集成电路（100）的一部分的数据处理器电路。

公开(公告)号：US5592405A

公开(公告)日：1997-01-07

申请号：US484579

申请日：1995-06-07

申请人： Robert J. Gove ,  Karl M. Guttag ,  Keith Balmer ,  Nicholas K. Ing-Simmons

发明人： Robert J. Gove ,  Karl M. Guttag ,  Keith Balmer ,  Nicholas K. Ing-Simmons

IPC分类号： G06F15/167 ,  G06F12/02 ,  G06F12/06 ,  G06F15/173 ,  G06F15/80 ,  G06F7/38 ,  G06F7/00 ,  G06F7/50

CPC分类号： G06F15/17375 ,  G06F12/0284

摘要： A data processing apparatus includes an arithmetic logic unit is divided into a plurality of sections. Each section generates at a corresponding output a digital resultant signal representing a combination of respective subsets of first and second multibit digital inputs. The arithmetic logic unit includes a status detector generating a single bit status signal indicative of said digital resultant signal of a corresponding section of the arithmetic logic unit. These single bit status signals are stored in predetermined locations within a multiple flags register. An options register stores an indication of the number of sections selected from a plurality of possible number of sections into which the arithmetic logic unit is divided. The arithmetic logic unit is further connected to the multiple flags register so that each section selects for output either corresponding bits of the first multibit digital input or the second multibit digital input dependent upon the digital state of a corresponding single status bit in the multiple flags register. This technique permits a variety of functions such as add with saturation, maximum, pixel transparency and color expansion.

摘要翻译： 一种数据处理装置，包括被分成多个部分的算术逻辑单元。 每个部分在相应的输出处产生表示第一和第二多位数字输入的各个子集的组合的数字结果信号。 算术逻辑单元包括状态检测器，其产生指示算术逻辑单元的相应部分的所述数字结果信号的单位状态信号。 这些单位状态信号存储在多标志寄存器内的预定位置。 选项寄存器存储从算术逻辑单元划分到的多个可能数量的区段中选择的区段数量的指示。 算术逻辑单元还连接到多标志寄存器，使得每个部分选择输出第一多位数字输入或第二多位数字输入的对应位，取决于多标志寄存器中对应的单个状态位的数字状态 。 这种技术允许各种功能，如饱和度，最大值，像素透明度和颜色扩展等。

公开(公告)号：US5590350A

公开(公告)日：1996-12-31

申请号：US159282

申请日：1993-11-30

申请人： Karl M. Guttag ,  Keith Balmer ,  Robert J. Gove ,  Christopher J. Read ,  Jeremiah E. Golston ,  Sydney W. Poland ,  Nicholas Ing-Simmons ,  Philip Moyse

发明人： Karl M. Guttag ,  Keith Balmer ,  Robert J. Gove ,  Christopher J. Read ,  Jeremiah E. Golston ,  Sydney W. Poland ,  Nicholas Ing-Simmons ,  Philip Moyse

IPC分类号： G06F7/57 ,  G06F9/00 ,  H03K19/00

CPC分类号： G06F7/57

摘要： A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. A controllable shifter is an alternative to the barrel rotator (235). The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default barrel rotate amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.

摘要翻译： 数据处理装置包括产生由功能信号选择的三个输入的组合的三输入算术逻辑单元（230）。 数据寄存器（200）存储三个数据输入和算术逻辑单元输出。 第二输入信号来自可控筒旋转器（235）。 旋转量是存储在特殊数据寄存器中的默认旋转量，从数据寄存器或零调用的预定数据位组。 恒定源（236）连接到筒旋转器（235）以提供“1”的多位数字信号。 这允许产生形式2N的第二输入信号，其中N是旋转量。 桶旋转器（235）的输出可以独立于算术逻辑单元（230）的结果存储。 可控制的换档器是桶旋转器（235）的替代品。 第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。 掩模的一个优选形式具有对应于掩模输入信号的许多右对齐1。 该掩模输入信号可以是由多路复用器选择的默认桶旋转量或第三输入信号的预定数量的最低有效位。 选择掩模的第二优选形式是从数据寄存器回调的数据的最低有效位的预定集合的最左1，最右1，最左位变化或最右位变化中的一个。 在本发明的优选实施例中，三输入算术逻辑单元（230）被实现为作为在图像处理中使用的多处理器集成电路（100）的一部分的数据处理器电路。

公开(公告)号：US5512896A

公开(公告)日：1996-04-30

申请号：US159359

申请日：1993-11-30

申请人： Christopher J. Read ,  Karl M. Guttag

发明人： Christopher J. Read ,  Karl M. Guttag

IPC分类号： H03M7/42 ,  H03M7/40

CPC分类号： H03M7/42

摘要： A data processor Huffman encodes a series of multibit signed digital numbers determining the needed data size by detecting the bit position of the greatest significant bit that differs from the most significant bit. Either a left most bit change detector (237) determines this bit position or a left most one detector (237) determines this bit position from the absolute value of the multibit signed digital number. A set of least significant bits equal in number to the data size are selected from the multibit signed digital number. The data processor formed the Huffman encoded signal by concatenating the data size and the selected least significant bits if the original multibit signed digital number was greater than or equal to zero, or by concatenating the data size with the sum of the selected bits and a multibit digital constant having a number of "1's" equal to the data size. A Huffman encoded string of data is formed by concatenating Huffman encoded signals of the next multibit signed digital number with Huffman encoded signals of prior multibit signed digital numbers in the series. This invention is preferably practiced using a data processing circuit (71) having a three input arithmetic logic unit (230), a status register (210), a barrel rotator (235), either a left most bit change detector or a left most one detector (237) and a mask generator (239).

摘要翻译： 数据处理器霍夫曼通过检测与最高有效位不同的最大有效位的位位置，对一系列多位有符号数字数字进行编码，从而确定所需的数据大小。 最左位更改检测器（237）确定该位位置，或者最左一个检测器（237）从多位有符号数字数字的绝对值确定该位位置。 从多位有符号数字数字中选择与数据大小相等的一组最低有效位。 数据处理器通过连接数据大小和所选择的最低有效位来形成霍夫曼编码信号，如果原始多位有符号数字数字大于或等于零，或者通过连接数据大小与所选择的比特和多位数 具有等于​​数据大小的数字“1”的数字常数。 霍夫曼编码的数据串通过将下一个多位有符号数字数字的霍夫曼编码信号与该系列中的先前多位符号数字数字的霍夫曼编码信号相连而形成。 本发明优选地使用具有三输入算术逻辑单元（230），状态寄存器（210），桶旋转器（235），左最左位更改检测器或最左一位 检测器（237）和掩模发生器（239）。

公开(公告)号：US5493524A

公开(公告)日：1996-02-20

申请号：US426992

申请日：1995-04-24

申请人： Karl M. Guttag ,  Richard D. Simpson ,  Brendan Walsh

发明人： Karl M. Guttag ,  Richard D. Simpson ,  Brendan Walsh

IPC分类号： G06F7/50 ,  G06F7/509 ,  G06F7/575 ,  G06F9/302 ,  G06F9/305

CPC分类号： G06F7/509 ,  G06F7/575 ,  G06F9/30014 ,  G06F9/30029

摘要： A three input arithmetic logic unit (230) forms a mixed arithmetic and Boolean combination of three multibit input signals. The current instruction drives an instruction decoder (250, 245) that generates functions signals F0-F7 which control the combination formed. The three input arithmetic logic unit (230) preferably employs a set of bit circuits (400), each forming carry propagate, generate and kill signals. These signals and a carry input produce a bit resultant and a carry output to the next bit circuit. Selection of the function signals enables the combination to be insensitive to one of the input signals, thus performing a two input function of remaining input signals. The instruction itself may include the function signals and function modification bits, or the function signals and function modification signals may be stored in a special data register. Function modification signals cause modification of the function signals prior to use. The three input arithmetic logic unit (230) includes a least significant bit carry-in generator (246) supplying a carry input to the least significant bit circuit (400). This carry input is determined by the combination being formed, and generally is "1" only during subtraction. The carry input may be specified in the special purpose data register (D0) for certain instructions.

摘要翻译： 三输入算术逻辑单元（230）形成三个多位输入信号的混合运算和布尔组合。 当前指令驱动产生控制所形成的组合的功能信号F0-F7的指令译码器（250,245）。 三输入算术逻辑单元（230）优选地采用一组比特电路（400），每一组形成进位传播，产生和终止信号。 这些信号和进位输入产生一个比特结果和一个进位输出到下一个比特电路。 功能信号的选择使得组合对输入信号之一不敏感，从而执行剩余输入信号的两个输入功能。 指令本身可以包括功能信号和功能修改位，或者功能信号和功能修改信号可以存储在特殊数据寄存器中。 功能修改信号在使用前会引起功能信号的修改。 三输入算术逻辑单元（230）包括向最低有效位电路（400）提供进位输入的最低有效位进位发生器（246）。 该进位输入由形成的组合确定，并且通常在减法期间为“1”。 某些指令可以在专用数据寄存器（D0）中指定进位输入。

公开(公告)号：US5487146A

公开(公告)日：1996-01-23

申请号：US209124

申请日：1994-03-08

申请人： Karl M. Guttag ,  Sydney W. Poland ,  Keith Balmer ,  Robert J. Gove ,  Christopher J. Read

发明人： Karl M. Guttag ,  Sydney W. Poland ,  Keith Balmer ,  Robert J. Gove ,  Christopher J. Read

IPC分类号： G06F13/28 ,  G09G5/393 ,  G06F12/06

CPC分类号： G06F13/28 ,  G09G5/393

摘要： A data processing device includes a memory, a control circuit, a guide table and an address generating circuit. The control circuit receives a packet transfer request and packet transfer parameters. The packet transfer parameters include a start address, dimension values defining a block of addresses, guide table having guide table entries and a table pointer. Each guide table entry has an address value. The table pointer initially points to a first guide table entry in the guide table. The address generating circuit forms a set of a block of addresses for memory access corresponding to each guide table entry, having a start address from a predetermined combination of the start address and the address value of the guide table entry. The block of addresses are formed from the dimension values. Following the memory accesses, the address generating circuit updates the table pointer to point to a next entry in the guide table. The address generating circuit may add the address value to the prior block starting address or add the guide table value to the starting address. The memory access may be a memory read from the block of addresses or a memory write to the block of addresses.

摘要翻译： 数据处理装置包括存储器，控制电路，引导表和地址产生电路。 控制电路接收分组传送请求和分组传送参数。 分组传送参数包括起始地址，定义地址块的维度值，具有指导表条目的指南表和表指针。 每个指南表项具有地址值。 表指针最初指向指南表中的第一个指南表项。 地址生成电路形成与每个指导表条目对应的用于存储器访问的地址块的集合，具有来自引导表条目的起始地址和地址值的预定组合的起始地址。 地址块由维度值形成。 在存储器访问之后，地址产生电路更新表指针以指向指南表中的下一条目。 地址产生电路可以将地址值添加到先前块开始地址，或者将引导表值添加到起始地址。 存储器访问可以是从地址块读取的存储器或写入地址块的存储器。

公开(公告)号：US5485411A

公开(公告)日：1996-01-16

申请号：US159345

申请日：1993-11-30

申请人： Karl M. Guttag ,  Richard Simpson ,  Brendan Walsh

发明人： Karl M. Guttag ,  Richard Simpson ,  Brendan Walsh

IPC分类号： G06F7/575 ,  G06F7/38

CPC分类号： G06F7/575

摘要： A three input arithmetic logic unit (230) forms a mixed arithmetic and Boolean combination of three multibit input signals. The arithmetic logic unit (230) first forms a Boolean combination and then forms an arithmetic combination. The current instruction drives an instruction decoder (250, 245) that generates the functions signals F0-F7 which control the combination formed. The three input arithmetic logic unit (230) preferably employs a set of bit circuits (400), each forming carry propagate, generate and kill signals. These signals may employed with a multilevel logic tree circuit and a carry input to produce a bit resultant and a carry output to the next bit circuit. This structure permits formation of selected arithmetic, Boolean or mixed arithmetic and Boolean function of the three input signals based upon the current instruction. Selection of the function signals enables the combination to be insensitive to one of the input signals, thus performs a two input function of remaining input signals. The instruction itself may include the function signals and function modification bits, or the function signals and function modification signals may be stored in a special data register. Function modification signals cause modification of the function signals prior to use. The three input arithmetic logic unit (230) includes a least significant bit carry-in generator (246) supplying a carry input to the least significant bit. This carry input is determined by the combination being formed, and generally is "1" only during subtraction. The carry input may be specified in the special purpose data register (D0) for certain instructions. The combination formed is optionally modified dependent upon the sign bit of one of the inputs.

摘要翻译： 三输入算术逻辑单元（230）形成三个多位输入信号的混合运算和布尔组合。 算术逻辑单元（230）首先形成布尔组合，然后形成算术组合。 当前指令驱动产生控制所形成的组合的功能信号F0-F7的指令译码器（250,245）。 三输入算术逻辑单元（230）优选地采用一组比特电路（400），每一组形成进位传播，产生和终止信号。 这些信号可以与多级逻辑树电路和进位输入一起使用，以产生位结果和进位输出到下一位电路。 该结构允许基于当前指令形成三个输入信号的所选算术，布尔或混合运算和布尔函数。 功能信号的选择使得组合对输入信号之一不敏感，从而执行剩余输入信号的两个输入功能。 指令本身可以包括功能信号和功能修改位，或者功能信号和功能修改信号可以存储在特殊数据寄存器中。 功能修改信号在使用前会引起功能信号的修改。 三输入算术逻辑单元（230）包括向最低有效位提供进位输入的最低有效位进位发生器（246）。 该进位输入由形成的组合确定，并且通常在减法期间为“1”。 某些指令可以在专用数据寄存器（D0）中指定进位输入。 根据其中一个输入的符号位可选地修改形成的组合。

公开(公告)号：US5333261A

公开(公告)日：1994-07-26

申请号：US59006

申请日：1993-05-07

申请人： Karl M. Guttag ,  Michael D. Asal ,  Neil Tebbutt ,  Mark F. Novak

发明人： Karl M. Guttag ,  Michael D. Asal ,  Neil Tebbutt ,  Mark F. Novak

IPC分类号： G06F9/345 ,  G06F9/38 ,  G06F15/78 ,  G06T1/20 ,  G06F15/20

CPC分类号： G06F9/345 ,  G06F15/7857 ,  G06F9/3885 ,  G06T1/20

摘要： The graphics processing apparatus of the present invention utilizes individual registers of a register file to store the X and Y coordinates of pixels. These X and Y coordinates though formed into a single data word are separable by, for example, having the most significant bits specifying the Y coordinate and the least significant bits specifying the Y coordinate. The graphics processing apparatus supports instructions which provide separate and independent data manipulation of these X and Y coordinates. These X Y coordinate manipulation instructions can provide for separate X Y arithmetic operations on two data words, separate X and Y compare operations, separate X and Y data move operations and a conversion between the X Y address form to the linear address form. This technique is highly useful for manipulation of X Y address coordinates in a visual display system employing bit mapped graphics.

摘要翻译： 本发明的图形处理装置利用寄存器文件的各个寄存器来存储像素的X和Y坐标。 这些X和Y坐标虽然形成单个数据字，但是可以通过例如具有指定Y坐标的最高有效位和指定Y坐标的最低有效位来分离。 图形处理装置支持提供对这些X和Y坐标的单独且独立的数据操纵的指令。 这些X Y坐标操作指令可以为两个数据字提供单独的X Y算术运算，分别进行X和Y比较运算，单独的X和Y数据移动操作以及X Y地址格式与线性地址格式之间的转换。 该技术对于使用位映射图形的可视显示系统中的X Y地址坐标的操纵非常有用。

公开(公告)号：US5270973A

公开(公告)日：1993-12-14

申请号：US563471

申请日：1990-08-06

申请人： Andre J. Guillemaud ,  Anthony M. Balistreri ,  Karl M. Guttag ,  Richard D. Simpson

发明人： Andre J. Guillemaud ,  Anthony M. Balistreri ,  Karl M. Guttag ,  Richard D. Simpson

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1006 ,  G11C7/1075

摘要： A video random access memory includes memory cells arranged in rows and columns. The columns of memory cells are divided into first and second portions, and the cells of each row of the first portion of memory are interleaved by address with the cells of the same row of the second portion of memory. A first half of a serial register includes a plurality of storage elements that are interleaved by address with a plurality of storage elements of a second half of the serial register. Between the first and second portions of the memory cells, column leads and a multiplexer selectively couple data from either the first portion or the second portion of the columns of the memory cells to either the first half or the second half of the serial register.

摘要翻译： 视频随机存取存储器包括以行和列排列的存储单元。 存储器单元的列被分成第一和第二部分，并且存储器的第一部分的每行的单元通过与存储器的第二部分的同一行的单元的地址进行交织。 串行寄存器的前半部分包括多个存储元件，其通过地址与串行寄存器的后半部分的多个存储元件进行交织。 在存储器单元的第一和第二部分之间，列引线和多路复用器选择性地将数据从存储器单元的列的第一部分或第二部分耦合到串行寄存器的前半部分或后半部分。