公开(公告)号：US5987619A

公开(公告)日：1999-11-16

申请号：US947372

申请日：1997-10-08

申请人： Takeshi Hamamoto ,  Masaki Tsukude

发明人： Takeshi Hamamoto ,  Masaki Tsukude

IPC分类号： G11C11/407 ,  G06F1/10 ,  G11C11/409 ,  G06F1/04

CPC分类号： G06F1/10

摘要： An input signal phase compensation circuit having a monitor mode and a normal operation mode includes a mode switching circuit, a logic gate receiving an internal data signal, a delay circuit connected to the logic gate, and a phase comparator comparing, in the monitor mode, phases of a signal output from the delay circuit and a clock signal, and determining time for delaying an internal clock signal in a variable delay circuit so as to match phases of the both signals. In the normal operation mode, the time is fixed, and data is obtained at phase compensated timing.

摘要翻译： 具有监视模式和正常操作模式的输入信号相位补偿电路包括模式切换电路，接收内部数据信号的逻辑门，连接到逻辑门的延迟电路，以及在监视器模式下， 从延迟电路输出的信号的相位和时钟信号，以及确定用于延迟可变延迟电路中的内部时钟信号的时间，以便匹配两个信号的相位。 在正常工作模式下，时间是固定的，并且在相位补偿定时获得数据。

公开(公告)号：US5982698A

公开(公告)日：1999-11-09

申请号：US215927

申请日：1998-12-18

申请人： Masaki Tsukude

发明人： Masaki Tsukude

IPC分类号： G11C11/401 ,  G11C7/06 ,  G11C8/00 ,  G11C8/12 ,  G11C11/407 ,  G11C11/409

CPC分类号： G11C7/06 ,  G11C8/12

摘要： A semiconductor integrated circuit device of the present invention includes a plurality of banks and a plurality of sense amplifier bands. A switch circuit included in each sense amplifier band receives a signal on a transmission line and outputs a signal read from the bank to a global data input/output line arranged in the column direction. A column bank control circuit for outputting a column bank control signal is arranged on the column decoder side. The column bank control signal is supplied to the transmission line through a column bank control signal line arranged in the column direction. The switch circuit operates in accordance with the column bank control signal. By such a configuration, a column-related operation can be matched easily.

摘要翻译： 本发明的半导体集成电路器件包括多个堤和多个读出放大器带。 包括在每个读出放大器带中的开关电路接收传输线上的信号，并将从存储体读出的信号输出到沿列方向布置的全局数据输入/输出线。 用于输出列组控制信号的列组控制电路被布置在列解码器侧。 列列控制信号通过沿列方向布置的列组控制信号线提供给传输线。 开关电路根据列组控制信号进行工作。 通过这样的配置，可以容易地匹配列相关操作。

公开(公告)号：US5949731A

公开(公告)日：1999-09-07

申请号：US941215

申请日：1997-09-30

申请人： Masaki Tsukude

发明人： Masaki Tsukude

IPC分类号： G01R31/28 ,  G01R31/30 ,  G11C5/00 ,  G11C11/401 ,  G11C11/407 ,  G11C29/06 ,  G11C8/00

CPC分类号： G11C29/06 ,  G11C29/12005 ,  G11C29/26 ,  G11C29/34 ,  G11C29/50 ,  G11C5/00 ,  G11C11/401 ,  G11C2029/1202 ,  G11C2029/2602

摘要： Current is reduced in driving a word line in stress acceleration testing such as burn-in, and the time required for the stress acceleration testing is reduced. For an address signal applied from an address buffer, a predetermined internal address signal bit is degenerated and a remaining address signal bit is rendered valid in response to an activation of a stress acceleration mode designation signal to simultaneously drive a desired number of word lines of all word lines to selected state. Any number of word lines can be simultaneously selected and hence current flowing in driving word lines can be reduced in the stress acceleration mode. In the stress acceleration mode of operation, bit line voltage and cell plate voltage are changed, and a current required for driving a plurality of word lines into a selected state is limited.

公开(公告)号：US5896328A

公开(公告)日：1999-04-20

申请号：US31556

申请日：1998-02-27

申请人： Tetsushi Tanizaki ,  Masaki Tsukude

发明人： Tetsushi Tanizaki ,  Masaki Tsukude

IPC分类号： G11C11/401 ,  G11C11/409 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/83 ,  G11C29/84

摘要： In a defective cell write mode, a precharge potential generating circuit generates a precharge potential at a high level or a low level in accordance with an external control signal, and applies the potential to a bit line pair. Parallel to a fuse element provided between a main bit line precharge potential supply line and a sub bit line precharge potential supply line and is cut when a column is replaced by a redundancy column of memory cells, a pass transistor which is rendered conductive in the defective cell write mode is provided.

摘要翻译： 在有缺陷的单元写入模式中，预充电电位产生电路根据外部控制信号产生高电平或低电平的预充电电位，并将电位施加到位线对。 平行于位于主位线预充电电位供给线和副位线预充电电位供给线之间的熔丝元件，并且当列被存储单元的冗余列代替时被切断，在缺陷中导通的通过晶体管 提供单元写入模式。

公开(公告)号：US5848012A

公开(公告)日：1998-12-08

申请号：US841139

申请日：1997-04-24

申请人： Masaki Tsukude ,  Takahiro Tsuruda

发明人： Masaki Tsukude ,  Takahiro Tsuruda

IPC分类号： G11C11/409 ,  G11C7/12 ,  G11C7/18 ,  G11C11/401 ,  G11C11/4094 ,  G11C11/4097 ,  G11C5/02 ,  G11C5/06

CPC分类号： G11C11/4097 ,  G11C11/4094 ,  G11C7/12 ,  G11C7/18

摘要： A semiconductor memory device comprises a main bit line pair, a plurality of subbit line pairs, a plurality of selection transistor pairs, a plurality of word lines, a plurality of memory cells, and a plurality of first precharging circuits. The subbit line pairs are provided in correspondence to the main bit line pair. One and other subbit lines of the subbit line pairs are arranged in straight lines along the main bit line pair. The selection transistors are provided in correspondence to the subbit line pairs. Each of the selection transistor pairs is connected between the main bit line pair and the corresponding subbit line pair, and turned on in response to a prescribed selection signal. The word lines are arranged to intersect with one and the other subbit lines of the subbit line pairs. The memory cells are provided in correspondence to intersection points between one and the other subbit lines of the subbit line pairs and the word lines. Each of the memory cells is connected to the corresponding subbit line and the corresponding word line. The first precharging circuits are provided in correspondence to the subbit line pairs. Each of the first precharging circuits directly precharges the corresponding subbit line pair at the prescribed precharging potential.

摘要翻译： 半导体存储器件包括主位线对，多个子行对，多个选择晶体管对，多个字线，多个存储单元和多个第一预充电电路。 对应于主位线对提供子行对。 子列线对中的一个和其它子条线沿着主位线对排列成直线。 选择晶体管对应于子线对设置。 每个选择晶体管对连接在主位线对和对应的子行对之间，并响应于规定的选择信号而导通。 字线布置成与子线对的一个和另一个子行线相交。 存储单元对应于子行对和字线的一个和另一个子行之间的交点。 每个存储单元连接到相应的子行和相应的字线。 第一预充电电路对应于子线对设置。 每个第一预充电电路以预定的预充电电压直接对相应的子
线对进行预充电。

公开(公告)号：US5831924A

公开(公告)日：1998-11-03

申请号：US711331

申请日：1996-09-06

申请人： Yasuhiko Nitta ,  Masaki Tsukude

发明人： Yasuhiko Nitta ,  Masaki Tsukude

IPC分类号： G11C11/413 ,  G11C7/18 ,  G11C8/14 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C8/00

CPC分类号： G11C8/14 ,  G11C7/18

摘要： One memory array is divided into a plurality of banks sharing a row of memory cells. Global IO buses are disposed for memory column blocks forming the plurality of banks included in one memory array. The global IO buses are selectively and electrically connected to the same data input/output terminal.

摘要翻译： 一个存储器阵列被分成共享一行存储器单元的多个存储体。 全局IO总线被布置用于形成包括在一个存储器阵列中的多个存储体的存储器列块。 全局IO总线选择性地电连接到相同的数据输入/输出端子。

公开(公告)号：US5831921A

公开(公告)日：1998-11-03

申请号：US895064

申请日：1997-07-16

申请人： Masaki Tsukude

发明人： Masaki Tsukude

IPC分类号： G11C11/403 ,  G11C11/401 ,  G11C11/406 ,  G11C11/407 ,  G11C11/408 ,  G11C11/409 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C11/408

摘要： In a DRAM, an upper address is assigned to each of ways W0 and W1, and a lower address is assigned to each word line WL in each of ways W0 and W1. A self-refresh start trigger generating circuit senses start of self-refresh, and a refresh address change sensing circuit senses change in an upper address. Based on the result of sensing, way selection signals RX0 and RX1 will not be reset and held at an active level while ways W0 and W1 are selected, respectively. Consequently, power consumption can be reduced compared to a conventional example in which signals RX0 and RX1 are reset every time a single word line WL is selected.

摘要翻译： 在DRAM中，向W0和W1的每一种分配上部地址，并且以W0和W1的方式将每个字线WL分配较低的地址。 自刷新开始触发发生电路感测自刷新的开始，刷新地址变化感测电路感测到上部地址的变化。 基于感测的结果，方式选择信号RX0和RX1将不会被复位并保持在有效电平，而W0和W1分别被选择。 因此，与每当选择单个字线WL时信号RX0和RX1被复位的常规示例相比，能够降低功耗。

公开(公告)号：US5815428A

公开(公告)日：1998-09-29

申请号：US893045

申请日：1997-07-14

申请人： Takahiro Tsuruda ,  Masaki Tsukude

发明人： Takahiro Tsuruda ,  Masaki Tsukude

IPC分类号： G11C11/401 ,  G11C7/18 ,  G11C11/34 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C5/06

CPC分类号： G11C7/18 ,  G11C11/4097 ,  H01L27/10805

摘要： A semiconductor memory device includes a semiconductor substrate, a plurality of sub bit line pairs formed on the semiconductor substrate, a main bit line pair formed at a layer above the plurality of sub bit line pairs, a plurality of selecting transistors, a plurality of word lines located to cross the sub bit line pairs, and a plurality of memory cells. Each selecting transistor is provided corresponding to one sub bit line and has one source/drain region connected to a corresponding sub bit line. At a layer above the other source/drain region of the selecting transistor, an intermediate layer is formed in the same layer as that of a storage node of memory cell. The intermediate layer is connected to the other source/drain region of the selecting transistor through a contact hole formed beneath it. The intermediate layer is further connected to the main bit line through another contact hole formed on the intermediate layer.

摘要翻译： 半导体存储器件包括半导体衬底，形成在半导体衬底上的多个子位线对，在多个子位线对之上形成的主位线对，多个选择晶体管，多个字 位于与子位线对交叉的线，以及多个存储单元。 每个选择晶体管对应于一个子位线提供，并且具有连接到相应的子位线的一个源极/漏极区域。 在选择晶体管的另一个源极/漏极区之上的层上，在与存储单元的存储节点相同的层中形成中间层。 中间层通过形成在其上的接触孔连接到选择晶体管的另一个源/漏区。 中间层通过形成在中间层上的另一个接触孔进一步连接到主位线。

公开(公告)号：US08061895B2

公开(公告)日：2011-11-22

申请号：US12362495

申请日：2009-01-30

申请人： Masaki Tsukude

发明人： Masaki Tsukude

IPC分类号： G01K7/00 ,  G11C7/04 ,  H03K17/14

CPC分类号： G01K7/015 ,  G01K3/005

摘要： There is provided a semiconductor device which can maintain a high tuning accuracy while suppressing a cost increase and suppress an increase in the time required for tuning. There are included, in addition to variable resistors configuring a level shift circuit, an additional resistor coupled between the output node of a VBGR voltage of a BGR circuit and one of the variable resistors and an additional resistor coupled between the other of the variable resistors and a reference voltage. N-channel MOS transistors are coupled in parallel with the additional resistors, respectively.

摘要翻译： 提供一种能够在抑制成本增加的同时保持高调谐精度并抑制调谐所需时间的增加的半导体装置。 除了构成电平移位电路的可变电阻器之外，还包括耦合在BGR电路的VBGR电压的输出节点和可变电阻器之一的附加电阻器以及耦合在另一个可变电阻器之间的附加电阻器，以及 参考电压。 N沟道MOS晶体管分别与附加电阻并联耦合。

公开(公告)号：US20060209611A1

公开(公告)日：2006-09-21

申请号：US11375079

申请日：2006-03-15

申请人： Masaki Tsukude

发明人： Masaki Tsukude

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40615 ,  G11C2211/4061 ,  G11C2211/4067

摘要： In a DRAM having a complete hidden refresh function, when data refresh is to be carried out in an active mode, a signal for selecting a way is set to an “H” level and then reset to an “L” level at each cycle while the corresponding upper address is designated. When data refresh is to be carried out in a standby mode, the signal for selecting the way is maintained at an “H” level and is not reset to an “L” level while the corresponding upper address is designated. This can reduce the standby current.

摘要翻译： 在具有完全隐藏刷新功能的DRAM中，当在活动模式下执行数据刷新时，用于选择路径的信号被设置为“H”电平，然后在每个周期重置为“L”电平 指定相应的上位地址。 当在待机模式下进行数据更新时，选择路径的信号保持在“H”电平，并且在指定相应的上位地址时不会重置为“L”电平。 这可以减少待机电流。