公开(公告)号：US07582926B2

公开(公告)日：2009-09-01

申请号：US11289493

申请日：2005-11-30

申请人： Hiroshi Iwata ,  Akihide Shibata

发明人： Hiroshi Iwata ,  Akihide Shibata

IPC分类号： H01L29/76

CPC分类号： H01L29/66833 ,  B82Y10/00 ,  G11C16/0466 ,  H01L21/84 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/118 ,  H01L27/1203 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconductor storage device having: a first conductivity type region formed in a semiconductor layer; a second conductivity type region formed in the semiconductor layer in contact with the first conductivity type region; a memory functional element disposed on the semiconductor layer across the boundary of the first and second conductivity type regions; and an electrode provided in contact with the memory functional element and on the first conductivity type region via an insulation film, and a portable electronic apparatus comprising the semiconductor storage device. The present invention can fully cope with scale-down and high-integration by constituting a selectable memory cell substantially of one device.

摘要翻译： 本发明提供一种半导体存储装置，具有：形成在半导体层中的第一导电型区域; 形成在与第一导电类型区域接触的半导体层中的第二导电类型区域; 存储功能元件，设置在跨越第一和第二导电类型区域的边界的半导体层上; 以及通过绝缘膜与所述存储功能元件和所述第一导电类型区域接触地设置的电极，以及包括所述半导体存储装置的便携式电子设备。 本发明可以通过构成基本上由一个设备构成的可选存储单元来完全应对缩小和高集成度。

公开(公告)号：US07262992B2

公开(公告)日：2007-08-28

申请号：US10844525

申请日：2004-05-13

申请人： Akihide Shibata ,  Takayuki Ogura ,  Hiroshi Iwata

发明人： Akihide Shibata ,  Takayuki Ogura ,  Hiroshi Iwata

IPC分类号： G11C11/34 ,  G11C7/00

CPC分类号： H04R25/505 ,  H04R2225/41

摘要： A hearing aid comprising a data memory includes a plurality of semiconductor memory cells. The semiconductor memory cell has a gate insulating film formed on a semiconductor substrate, on a well region provided in the semiconductor substrate, or on a semiconductor film deposited on an insulator; a single gate electrode formed on the gate insulating film; two memory functional units formed on both sidewalls of the single gate electrode; a channel formation region formed under the single gate electrode; and first diffusion regions disposed on both sides of the channel formation region. The semiconductor memory cell is constituted so as to change an amount of currents flowing from one of the first diffusion regions to the other first diffusion region according to an amount of charges retained in the memory functional unit or a polarization vector when a voltage is applied to the gate electrode.

摘要翻译： 包括数据存储器的助听器包括多个半导体存储单元。 半导体存储单元具有形成在半导体衬底上的阱绝缘膜，设置在半导体衬底中的阱区或沉积在绝缘体上的半导体膜; 形成在栅极绝缘膜上的单个栅电极; 形成在单个栅电极的两个侧壁上的两个存储功能单元; 形成在单个栅电极下面的沟道形成区域; 以及设置在通道形成区域两侧的第一扩散区域。 半导体存储单元被构成为根据保存在存储功能单元中的电荷量或者施加电压时的极化矢量来改变从第一扩散区域之一流向另一个第一扩散区域的电流量 栅电极。

公开(公告)号：US07170789B2

公开(公告)日：2007-01-30

申请号：US11213927

申请日：2005-08-30

申请人： Hiroshi Iwata ,  Yoshifumi Yaoi ,  Akihide Shibata

发明人： Hiroshi Iwata ,  Yoshifumi Yaoi ,  Akihide Shibata

IPC分类号： G11C11/34 ,  G11C7/00

CPC分类号： G11C16/28 ,  G11C7/14

摘要： Characteristic fluctuation of a reference cell due to read disturb is prevented. A memory cell 27m and a reference cell 27r respectively have memory function bodies that are formed on both sides of a gate electrode and have a function to retain electric charge or polarization. The memory cell 27m can store independent information pieces in memory function bodies 27mr and 27ml located on both sides of the gate electrode and the independent information pieces are read therefrom. On the other hand, in the reference cell 27r, only the information piece stored in a memory function body 27rl located on one side of the gate electrode is referred to in a sense amplifier 22.

摘要翻译： 防止由于读取干扰引起的参考单元的特性波动。 存储单元27m和参考单元27r分别具有形成在栅电极的两侧上并具有保持电荷或极化的功能的记忆功能体。 存储单元27m可以将独立的信息块存储在位于栅电极两侧的存储器功能体27mr和27ml中，并从其中读取独立的信息。 另一方面，在参考单元27r中，在读出放大器22中仅参考存储在位于栅电极一侧的存储器功能体27r1中的信息片。

公开(公告)号：US07167402B2

公开(公告)日：2007-01-23

申请号：US10848481

申请日：2004-05-19

申请人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

发明人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

IPC分类号： G11C29/00 ,  G11C11/34

CPC分类号： G11C29/838 ,  G11C16/0475 ,  G11C16/22 ,  G11C29/785 ,  G11C29/787 ,  G11C29/789 ,  H01L29/42332 ,  H01L29/7887 ,  H01L29/7923

摘要： A semiconductor storage device includes a plurality of memory elements and a redundancy circuit. Each of the memory elements includes a gate electrode provided on a semiconductor layer, a gate insulating film intervening between the gate electrode and the semiconductor layer, a channel region provided under the gate electrode, diffusion regions respectively provided at both sides of the channel region, the diffusion regions having a conductivity type which is opposite a conductivity type of the channel region, and memory functioning members respectively provided at both sides of the gate electrode, the memory functioning members having a function of holding charge. The redundancy circuit addresses a single chip memory including cells associated with a plurality of redundant lines and includes a decoder for selecting a redundant row. The semiconductor storage device can permanently inactivate further programming of the redundancy circuit in order to prevent a user from performing inadvertent programming.

摘要翻译： 半导体存储装置包括多个存储元件和冗余电路。 每个存储元件包括设置在半导体层上的栅极电极，介于栅电极和半导体层之间的栅极绝缘膜，设置在栅电极下方的沟道区，分别设置在沟道区两侧的扩散区， 具有与沟道区的导电类型相反的导电类型的扩散区和分别设置在栅极两侧的存储功能元件，存储功能元件具有保持电荷的功能。 冗余电路解决包括与多条冗余线相关联的单元的单个芯片存储器，并且包括用于选择冗余行的解码器。 半导体存储设备可以永久地停用冗余电路的进一步编程，以防止用户执行无意编程。

公开(公告)号：US07161207B2

公开(公告)日：2007-01-09

申请号：US10840173

申请日：2004-05-05

申请人： Koji Hamaguchi ,  Masaru Nawaki ,  Yoshinao Morikawa ,  Hiroshi Iwata ,  Akihide Shibata

发明人： Koji Hamaguchi ,  Masaru Nawaki ,  Yoshinao Morikawa ,  Hiroshi Iwata ,  Akihide Shibata

IPC分类号： H01L29/79

CPC分类号： H01L29/66833 ,  G11C16/10 ,  G11C16/30 ,  H01L21/28282 ,  H01L29/7923

摘要： A computer system comprising: (A) a CPU; (B) a memory arrangement comprising: (i) a side-wall memory array including a plurality of side-wall memory transistors; (ii) a charge pump; (iii) a plurality of switching circuits; and (iv) logic circuitry; and (C) a system bus, wherein each of the side-wall memory transistors comprises: a gate electrode formed on a semiconductor layer with a gate insulating film formed on the semiconductor layer; a channel region formed below the gate electrode; a pair of diffusion regions formed on the both sides of the channel region and having a conductive type opposite to that of the channel region; and a pair of memory functional units formed on the both sides of the gate electrode and having a function of retaining charges.

摘要翻译： 一种计算机系统，包括：（A）CPU; （B）存储装置，包括：（i）包括多个侧壁存储晶体管的侧壁存储器阵列; （ii）电荷泵; （iii）多个开关电路; 和（iv）逻辑电路; 和（C）系统总线，其中每个侧壁存储晶体管包括：形成在半导体层上的栅电极，其上形成有在半导体层上的栅极绝缘膜; 形成在栅电极下方的沟道区; 一对扩散区，形成在沟道区的两侧，具有与沟道区相反的导电类型; 以及形成在栅电极的两侧并具有保持电荷的功能的一对记忆功能单元。

公开(公告)号：US20060244049A1

公开(公告)日：2006-11-02

申请号：US10529880

申请日：2003-10-02

申请人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Kei Tokui ,  Masaru Nawaki

发明人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Kei Tokui ,  Masaru Nawaki

IPC分类号： H01L29/792

CPC分类号： H01L21/28273 ,  G11C16/225 ,  H01L29/7887

摘要： A memory cell array employs a memory element as a memory cell. The memory element is constructed of a gate electrode formed via a gate insulation film on a semiconductor layer, a channel region arranged under the gate electrode, diffusion regions that are arranged on both sides of the channel region and have a conductive type opposite to that of the channel region, and memory function bodies that are arranged on both sides of the gate electrode and have a function to retain electric charges. When first and second power voltages VCC1 and VCC2 supplied from the outside are lower than a prescribed voltage, a rewrite command to a memory circuit 34 that includes the memory cell array is inhibited by a lockout circuit 33a. With this arrangement, there are provided a semiconductor storage device capable of achieving storage retainment of two bits or more per memory element and stable operation even if the device is miniaturized and preventing the occurrence of a malfunction of rewrite error and so on attributed to a reduction in the power voltage supplied from the outside and a control method therefor.

摘要翻译： 存储单元阵列采用存储元件作为存储单元。 存储元件由在半导体层上形成的栅极绝缘膜，配置在栅电极下方的沟道区域形成的栅极电极构成，扩散区域配置在沟道区域的两侧，具有与 沟道区域和存储器功能体，其布置在栅电极的两侧并具有保持电荷的功能。 当从外部提供的第一和第二电源电压VCC 1和VCC 2低于规定电压时，由锁存电路33a禁止包括存储单元阵列的存储电路34的重写命令。 通过这种布置，提供了一种半导体存储装置，其能够实现每个存储元件的两位或更多的存储保持和稳定的操作，即使该装置小型化并且防止归因于减少的重写错误等的故障的发生 在外部提供的电源电压及其控制方法中。

公开(公告)号：US07129539B2

公开(公告)日：2006-10-31

申请号：US10844474

申请日：2004-05-13

申请人： Hiroshi Iwata ,  Takayuki Ogura ,  Akihide Shibata ,  Kouichirou Adachi

发明人： Hiroshi Iwata ,  Takayuki Ogura ,  Akihide Shibata ,  Kouichirou Adachi

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0491 ,  H01L21/28282 ,  H01L21/28291 ,  H01L21/76831 ,  H01L21/76897 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/6656 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor storage device includes a field effect transistor which has a gate insulator, a gate electrode and a pair of source/drain diffusion regions on a semiconductor substrate. The device also includes a coating film made of a dielectric having a function of storing electric charge and formed on the substrate in such a manner as to cover an upper surface and side surfaces of the gate electrode. The device further includes an interlayer insulator formed on and in contact with the coating film. The device still further includes contact members which extend vertically through the interlayer insulator and the coating film on the source/drain diffusion regions and which are electrically connected to the source/drain diffusion regions, respectively. The coating film and the interlayer insulator are made of materials which are selectively etchable to each other. Thus, the issues of overerase and read failures due to the overerase can be solved, and the device reliability can be enhanced.

公开(公告)号：US07092295B2

公开(公告)日：2006-08-15

申请号：US10847626

申请日：2004-05-18

申请人： Yasuaki Iwase ,  Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

发明人： Yasuaki Iwase ,  Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

IPC分类号： G11C16/04

CPC分类号： G11C29/50004 ,  G11C16/04 ,  G11C29/50 ,  G11C2029/0403 ,  G11C2029/5002

摘要： A semiconductor memory device includes a controller programming a nonvolatile memory cell by applying a first pulse so that a charge amount smaller than a target charge amount is accumulated in the nonvolatile memory cell, a second pulse train so that a second charge amount smaller than the target charge amount and larger than the first charge amount is accumulated in the nonvolatile memory cell, and a third pulse train so that a third charge amount falling within an allowable error range of the target charge amount is accumulated. The semiconductor memory cell includes a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode, diffusion regions disposed on both sides of the channel region and memory functional units formed on both sides of the gate electrode.

摘要翻译： 一种半导体存储器件包括：控制器，通过施加第一脉冲来编程非易失性存储器单元，使得小于目标电荷量的电荷量累积在非易失性存储单元中，第二脉冲串使得小于目标的第二电荷量 充电量大于第一充电量的电荷量累积在非易失性存储单元中，并且第三脉冲串使得落入目标充电量的容许误差范围内的第三充电量被累积。 半导体存储单元包括通过栅极绝缘膜形成在半导体层上的栅极电极，设置在栅电极下方的沟道区域，设置在沟道区域两侧的扩散区域和形成在栅电极两侧的存储功能单元 。

公开(公告)号：US07085166B2

公开(公告)日：2006-08-01

申请号：US10847587

申请日：2004-05-18

申请人： Yasuaki Iwase ,  Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

发明人： Yasuaki Iwase ,  Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

IPC分类号： G11C16/06

CPC分类号： G11C16/0475 ,  G11C16/10 ,  G11C16/28 ,  G11C16/3468 ,  G11C16/3477 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/66833 ,  H01L29/7887

摘要： A semiconductor memory device includes: a plurality of nonvolatile memory cells; a first load cell for generating a read voltage relative to a read current during reading from a selected nonvolatile memory cell; a reference cell for storing a reference state corresponding to a reference current of the selected nonvolatile memory cell; a second load cell for generating a voltage based on the reference current through the reference cell; and a programming circuit for generating a reference voltage equal to a voltage obtained from a specific current-voltage characteristic of the first load cell with respect to the reference current and programming the reference cell so as to equalize the voltage of the second load cell with the reference voltage, thereby to compensate for variations in the first load cell. And each of the nonvolatile memory cell includes a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges.

摘要翻译： 半导体存储器件包括：多个非易失性存储器单元; 用于在从所选择的非易失性存储器单元读取期间产生相对于读取电流的读取电压的第一测力传感器; 用于存储与所选择的非易失性存储单元的参考电流相对应的参考状态的参考单元; 第二测力传感器，用于基于通过参考单元的参考电流产生电压; 以及编程电路，用于生成等于从第一测力传感器的特定电流 - 电压特性获得的电压相对于参考电流的参考电压，并对参考单元进行编程，以便将第二测力传感器的电压与 参考电压，从而补偿第一测力传感器的变化。 并且每个非易失性存储单元包括通过栅极绝缘膜形成在半导体层上的栅极电极，设置在栅极电极下方的沟道区域，设置在沟道区域两侧的扩散区域，并且具有与 沟道区域和形成在栅极电极两侧的记忆功能单元，并具有保持电荷的功能。

公开(公告)号：US07064982B2

公开(公告)日：2006-06-20

申请号：US10844562

申请日：2004-05-13

申请人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

发明人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

IPC分类号： G11C16/04

CPC分类号： H01L29/792 ,  G11C16/0408 ,  H01L21/28282

摘要： A semiconductor memory device includes a memory cell including a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges; a switching transistor circuit including a negative voltage switching circuit for applying a negative voltage to the gate electrode of the memory cell, and a switching transistor connected to an output of the negative voltage switching circuit and a first voltage source for outputting a voltage having a voltage level lower than zero volt; a pull-up circuit connected to a control terminal of the switching transistor and selectively connected to a second voltage source for outputting a voltage having a voltage level higher than zero volt; and a pull-down circuit connected to the first voltage source and the control terminal of the switching transistor.

摘要翻译： 一种半导体存储器件包括：存储单元，包括通过栅极绝缘膜形成在半导体层上的栅极电极，设置在栅极电极下方的沟道区域，设置在沟道区域两侧的扩散区域，并且具有与该沟道区域相反的导电类型 以及形成在栅电极的两侧并具有保持电荷的功能的存储功能单元; 开关晶体管电路，包括用于向存储单元的栅电极施加负电压的负电压切换电路，以及连接到负电压开关电路的输出的开关晶体管和用于输出具有电压的电压的第一电压源 电平低于零伏; 连接到所述开关晶体管的控制端子并且选择性地连接到用于输出具有高于零伏的电压电平的电压的第二电压源的上拉电路; 以及连接到开关晶体管的第一电压源和控制端子的下拉电路。