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    Modify priority of dataset based on number of times the data set is processed by both a data detector circuit and a data decoder circuit
    61.
    发明授权
    Modify priority of dataset based on number of times the data set is processed by both a data detector circuit and a data decoder circuit 有权
    基于由数据检测器电路和数据解码器电路处理数据集的次数来修改数据集的优先级

    公开(公告)号：US09298369B2

    公开(公告)日：2016-03-29

    申请号：US13766874

    申请日：2013-02-14

    Applicant: LSI Corporation

    Inventor： Shaohua Yang ,  Fan Zhang ,  Jun Xiao ,  Kaitlyn T. Nguyen

    IPC: G06F9/46 ,  G06F3/06

    CPC classification number: G06F3/06 ,  G11B20/10009 ,  G11B20/10268 ,  G11B20/10305 ,  G11B20/10527

    Abstract: Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for quality based scheduling processing of data sets. In some cases, a priority indication associated with a data set is modified based upon one or more factors. As an example, the priority indication may be modified based upon a number of times that a given data set processed through both a data detector circuit and a data decoder circuit.

    Abstract translation: 与用于数据处理的系统和方法相关的系统，电路，设备和/或方法，更具体地涉及用于数据集的基于质量的调度处理的系统和方法。 在一些情况下，基于一个或多个因素修改与数据集相关联的优先指示。 作为示例，可以基于通过数据检测器电路和数据解码器电路来处理的给定数据集的次数来修改优先级指示。

    Systems and methods for skip layer data decoding
    62.
    发明授权
    Systems and methods for skip layer data decoding 有权
    跳过层数据解码的系统和方法

    公开(公告)号：US09214959B2

    公开(公告)日：2015-12-15

    申请号：US13770008

    申请日：2013-02-19

    Applicant: LSI Corporation

    Inventor： Shaohua Yang ,  Fan Zhang ,  Chung-Li Wang ,  Shu Li

    IPC: H03M13/00 ,  H03M13/11 ,  G11B20/18

    CPC classification number: H03M13/1122 ,  G11B20/1833 ,  H03M13/1128 ,  H03M13/114 ,  H03M13/1142 ,  H03M13/6331 ,  H03M13/6343 ,  H03M13/658

    Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding including skipping one or more codeword blocks in the data decoding process. In one embodiment a data processing system includes a skip control circuit operable to skip re-application of a data decode algorithm to a portion of a codeword where at least the number of unsatisfied checks for the portion is zero.

    Abstract translation: 本发明涉及用于数据处理的系统和方法，更具体地涉及用于执行数据解码的系统和方法，包括在数据解码过程中跳过一个或多个码字块。 在一个实施例中，数据处理系统包括跳过控制电路，该跳过控制电路可操作以跳过将数据解码算法重新应用于代码字的至少部分的不满足检查数为零的部分。

    Systems and methods for improved short media defect detection
    63.
    发明授权
    Systems and methods for improved short media defect detection 有权
    改进短介质缺陷检测的系统和方法

    公开(公告)号：US09110821B2

    公开(公告)日：2015-08-18

    申请号：US14243107

    申请日：2014-04-02

    Applicant: LSI Corporation

    Inventor： Weijun Tan ,  Fan Zhang ,  Shaohua Yang

    IPC: G06F11/10 ,  G11B20/10 ,  G11B20/18

    CPC classification number: G06F11/10 ,  G11B20/10009 ,  G11B20/10287 ,  G11B20/10296 ,  G11B20/1816 ,  G11B20/1883

    Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. As an example, a method is discusses that includes: receiving a decoded output including a first multi-bit symbol; receiving a detected output including a second multi-bit bit symbol; calculating values based upon respective combinations of the first multi-bit symbol and the second multi-bit symbols; calculating a first product and the second product based upon some of the aforementioned values; and asserting a suspect symbol indicator indicating a probability that the symbol is incorrect when at least one of the first product and the second product is negative.

    Abstract translation: 本发明的各种实施例提供了用于介质缺陷检测的系统和方法。 作为示例，讨论了一种方法，其包括：接收包括第一多位符号的解码输出; 接收包括第二多位位符号的检测输出; 基于第一多位符号和第二多位符号的相应组合计算值; 基于一些上述值计算第一产品和第二产品; 并且当第一产品和第二产品中的至少一个为负时，断定指示符号不正确的概率的可疑符号指示符。

    Min-sum based hybrid non-binary low density parity check decoder
    64.
    发明授权
    Min-sum based hybrid non-binary low density parity check decoder 有权
    基于最小和混合非二进制低密度奇偶校验解码器

    公开(公告)号：US09048874B2

    公开(公告)日：2015-06-02

    申请号：US13886103

    申请日：2013-05-02

    Applicant: LSI Corporation

    Inventor： Chung-Li Wang ,  Zongwang Li ,  Shu Li ,  Fan Zhang ,  Shaohua Yang

    IPC: H03M13/00 ,  H03M13/13 ,  H03M13/11

    CPC classification number: H03M13/13 ,  H03M13/1122 ,  H03M13/1125 ,  H03M13/1171 ,  H03M13/6583

    Abstract: An apparatus for decoding data includes a variable node processor, a check node processor, and a field transformation circuit. The variable node processor is operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages. The check node processor is operable to generate the check node to variable node messages and to calculate checksums based on variable node to check node messages. The variable node processor and the check node processor comprise different Galois fields. The field transformation circuit is operable to transform the variable node to check node messages from a first of the different Galois fields to a second of the Galois fields.

    Abstract translation: 用于解码数据的装置包括可变节点处理器，校验节点处理器和场变换电路。 可变节点处理器可操作以生成变量节点以检查节点消息，并且基于校验节点到可变节点消息来计算感知值。 校验节点处理器可用于将校验节点生成到可变节点消息，并且基于变量节点来计算校验和以检查节点消息。 可变节点处理器和校验节点处理器包括不同的伽罗瓦域。 场变换电路可操作以将变量节点变换为将来自不同伽罗瓦域中的第一个的节点消息校验到伽罗瓦域中的第二个。

    Low density parity check decoder with miscorrection handling
    65.
    发明授权
    Low density parity check decoder with miscorrection handling 有权
    低密度奇偶校验解码器与错误处理

    公开(公告)号：US08996969B2

    公开(公告)日：2015-03-31

    申请号：US13708941

    申请日：2012-12-08

    Applicant: LSI Corporation

    Inventor： Anatoli A. Bolotov ,  Shaohua Yang ,  Zongwang Li ,  Mikhail I Grinchuk ,  Lav D. Ivanovic ,  Fan Zhang ,  Yang Han

    IPC: H03M13/00 ,  H03M13/13 ,  H03M13/11

    CPC classification number: H03M13/13 ,  H03M13/1111 ,  H03M13/1142

    Abstract: A data processing system includes a decoder circuit, syndrome calculation circuit and hash calculation circuit. The decoder circuit is operable to apply a decoding algorithm to a decoder input based on a first portion of a composite matrix to yield a codeword. The syndrome calculation circuit is operable to calculate a syndrome based on the codeword and on the first portion of the composite matrix. The hash calculation circuit is operable to calculate a hash based on a second portion of the composite matrix. The decoder circuit is also operable to correct the codeword on the hash when the syndrome indicates that the codeword based on the first portion of the composite matrix is correct but a second test indicates that the codeword is miscorrected.

    Abstract translation: 数据处理系统包括解码器电路，校正子计算电路和散列计算电路。 解码器电路可操作以基于复合矩阵的第一部分将解码算法应用于解码器输入以产生码字。 校正子计算电路可操作以基于码字和复合矩阵的第一部分来计算校正子。 散列计算电路可操作以基于复合矩阵的第二部分来计算散列。 当校验子指示基于复合矩阵的第一部分的码字是正确的但是第二测试指示码字被修正时，解码器电路还可操作以校正散列上的码字。

    Modified targeted symbol flipping for non-binary LDPC codes
    66.
    发明授权
    Modified targeted symbol flipping for non-binary LDPC codes 有权
    用于非二进制LDPC码的修改的目标符号翻转

    公开(公告)号：US08977926B2

    公开(公告)日：2015-03-10

    申请号：US13629726

    申请日：2012-09-28

    Applicant: LSI Corporation

    Inventor： Chung-Li Wang ,  Lei Chen ,  Fan Zhang ,  Shaohua Yang ,  Qi Qi

    IPC: H03M13/00 ,  G06F11/00 ,  H03M13/11 ,  H03M13/37

    CPC classification number: H03M13/1108 ,  H03M13/3738

    Abstract: A LDPC decoder includes a processor for targeted symbol flipping of suspicious bits in a LDPC codeword with unsatisfied checks. All combinations of check indices and variable indices are compiled and correlated into a pool of targeted symbol flipping candidates and returned along with symbol indices to a process that uses such symbol indices to identify symbols to flip in order to break a trapping set.

    Abstract translation: LDPC解码器包括用于不满足检查的LDPC码字中的可疑比特的目标符号翻转的处理器。 检查索引和可变索引的所有组合被编译并且相关联到目标符号翻转候选的池中，并且与符号索引一起返回到使用这样的符号索引来识别符号以便打破陷阱集合的过程。

    Sector failure prediction method and related system
    68.
    发明授权
    Sector failure prediction method and related system 有权
    部门故障预测方法及相关系统

    公开(公告)号：US08886991B2

    公开(公告)日：2014-11-11

    申请号：US13661201

    申请日：2012-10-26

    Applicant: LSI Corporation

    Inventor： Fan Zhang ,  Shaohua Yang

    IPC: G06F11/00 ,  G06F11/18

    CPC classification number: G06F11/008

    Abstract: A method and system is disclosed for identification and removal of a memory sector prone to failure. The method performs satisfaction checks on the memory sector and monitors and stores returned Unsatisfied Checks (USC) for analysis by a pattern recognition algorithm. Once a first global iteration is pattern matched with a second global iteration from the sector, the method determines the period of the repetitive pattern. The method then identifies, as the sector prone to failure, the sector having the defined pattern and period. Once identified, the method uses a power management scheme to remove the sector prone to failure from further use by the memory system and displays to a user the details of the action taken.

    Abstract translation: 公开了用于识别和去除容易发生故障的存储器扇区的方法和系统。 该方法对存储器部分进行满意度检查，并通过模式识别算法监视和存储返回的不满意检查（USC）以进行分析。 一旦第一次全局迭代模式与扇区的第二次全局迭代模式匹配，该方法确定重复模式的周期。 然后，该方法识别出具有定义的模式和周期的扇区作为易于发生故障的扇区。 一旦识别出来，该方法使用电源管理方案去除容易发生故障的扇区，以便存储器系统进一步使用，并向用户显示所采取的动作的细节。

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