公开(公告)号：US07221020B2

公开(公告)日：2007-05-22

申请号：US11000003

申请日：2004-12-01

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： H01L29/94

CPC分类号： H01L27/10876 ,  H01L27/10808 ,  H01L27/10811 ,  H01L27/10891 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/7834 ,  H01L29/7835

摘要： Self-aligned recessed gate structures and method of formation are disclosed. Field oxide area for isolation are first formed in a semiconductor substrate. A plurality of columns are defined in an insulating layer formed over the semiconductor substrate subsequent to which a thin sacrificial oxide layer is formed over exposed regions of the semiconductor substrate but not over the field oxide areas. A dielectric material is then provided on sidewalls of each column and over portions of the sacrificial oxide layer and of the field oxide areas. A first etch is conducted to form a first set of trenches within the semiconductor substrate and a plurality of recesses within the field oxide areas. A second etch is conducted to remove dielectric residue remaining on the sidewalls of the columns and to form a second set of trenches. Polysilicon is then deposited within the second set of trenches and within the recesses to form recessed conductive gates.

摘要翻译： 公开了自对准凹陷门结构和形成方法。 首先在半导体衬底中形成用于隔离的场氧化物区域。 多个列限定在形成在半导体衬底上的绝缘层中，接着在半导体衬底的暴露区域上形成薄的牺牲氧化物层，但不在场氧化物区域上。 然后在每列的侧壁和牺牲氧化物层和场氧化物区域的部分上方提供电介质材料。 进行第一蚀刻以在半导体衬底内形成第一组沟槽和在场氧化物区域内形成多个凹陷。 进行第二蚀刻以去除残留在柱的侧壁上的电介质残余物并形成第二组沟槽。 然后将多晶硅沉积在第二组沟槽内并在凹槽内形成凹陷的导电栅极。

公开(公告)号：US06977421B2

公开(公告)日：2005-12-20

申请号：US10371689

申请日：2003-02-20

申请人： Mark McQueen ,  Luan C. Tran ,  Chandra Mouli

发明人： Mark McQueen ,  Luan C. Tran ,  Chandra Mouli

IPC分类号： H01L21/28 ,  H01L21/8242 ,  H01L27/105 ,  H01L29/80

CPC分类号： H01L27/10873 ,  H01L21/28123 ,  H01L27/105 ,  H01L27/10882 ,  H01L27/10894

摘要： The invention includes a DRAM array having a structure therein which includes a first material separated from a second material by an intervening insulative material. The first material is doped to at least 1×1017 atoms/cm3 with n-type and p-type dopant. The invention also includes a semiconductor construction in which a doped material is over a segment of a substrate. The doped material has a first type majority dopant therein, and is electrically connected with an electrical ground. A pair of conductively-doped diffusion regions are adjacent the segment, and spaced from one another by at least a portion of the segment. The conductively-doped diffusion regions have a second type majority dopant therein. The invention also encompasses methods of forming semiconductor constructions.

摘要翻译： 本发明包括其中具有结构的DRAM阵列，其包括通过中间绝缘材料与第二材料分离的第一材料。 第一种材料被掺杂至至少1×10 17个原子/ cm 3与n型和p型掺杂剂。 本发明还包括半导体结构，其中掺杂材料在衬底的一段上方。 掺杂材料在其中具有第一类型多数掺杂剂，并且与电接地电连接。 一对导电掺杂的扩散区域与该段相邻，并且通过该段的至少一部分彼此间隔开。 导电掺杂扩散区域中具有第二类型多数掺杂剂。 本发明还包括形成半导体结构的方法。

公开(公告)号：US06946353B2

公开(公告)日：2005-09-20

申请号：US10831192

申请日：2004-04-26

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L21/8234

CPC分类号： H01L29/66537 ,  H01L21/26586 ,  H01L21/823807 ,  H01L27/0922 ,  H01L29/1083

摘要： A method for adjusting Vt while minimizing parasitic capacitance for low voltage high speed semiconductor devices. The method uses shadow effects and an angled punch through prevention implant between vertical structures to provide a graded implant. The implant angle is greater than or equal to arc tangent of S/H where S is the horizontal distance between, and H is the height of, such vertical structures.

摘要翻译： 一种用于调节低电压高速半导体器件的寄生电容最小化的方法。 该方法使用阴影效应和倾斜冲击穿过垂直结构之间的预防植入物来提供分级植入物。 植入角度大于或等于S / H的反正切，其中S是水平距离，H是这种垂直结构的高度。

公开(公告)号：US06825077B2

公开(公告)日：2004-11-30

申请号：US10713647

申请日：2003-11-13

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： H01L218242

CPC分类号： H01L27/10873 ,  H01L27/0214 ,  H01L27/10894 ,  Y10S257/906 ,  Y10S438/981

摘要： The present invention includes a 6F2 DRAM array formed on a semiconductor substrate. The memory array includes a first memory cell. The first memory cell includes a first access transistor and a first data storage capacitor. A first load electrode of the first access transistor is coupled to the first data storage capacitor via a first storage node formed on the substrate. The memory array also includes a second memory cell. The second memory cell includes a second access transistor and a second data storage capacitor. A first load electrode of the second access transistor is coupled to the second data storage capacitor via a second storage node formed on the substrate. The first and second access transistors have a gate dielectric having a first thickness. The memory array further includes an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween. The isolation gate has a gate dielectric having a second thickness that is greater than the first thickness. The isolation gate dielectric may extend above or below a surface of the substrate.

摘要翻译： 本发明包括形成在半导体衬底上的6F 2 DRAM阵列。 存储器阵列包括第一存储单元。 第一存储单元包括第一存取晶体管和第一数据存储电容器。 第一存取晶体管的第一负载电极经由形成在衬底上的第一存储节点耦合到第一数据存储电容器。 存储器阵列还包括第二存储器单元。 第二存储单元包括第二存取晶体管和第二数据存储电容器。 第二存取晶体管的第一负载电极经由形成在基板上的第二存储节点耦合到第二数据存储电容器。 第一和第二存取晶体管具有具有第一厚度的栅极电介质。 存储器阵列还包括形成在第一和第二存储节点之间并被配置为在它们之间提供电隔离的隔离栅极。 隔离栅极具有第二厚度大于第一厚度的栅极电介质。 隔离栅极电介质可以在衬底的表面上方或下方延伸。

公开(公告)号：US06806137B2

公开(公告)日：2004-10-19

申请号：US10705707

申请日：2003-11-11

申请人： Luan C. Tran ,  Mark Durcan ,  Howard C. Kirsch

发明人： Luan C. Tran ,  Mark Durcan ,  Howard C. Kirsch

IPC分类号： H01L218242

CPC分类号： H01L27/10885 ,  H01L27/10814 ,  H01L27/10888

摘要： A memory device such as a 6F2 memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermost surface of the base substrate. A bit line contact strap electrically couples the bit line to the active area both along a vertical dimension of the bit line strap and along a horizontal dimension across the uppermost surface of the base substrate.

摘要翻译： 诸如6F 2存储器件的存储器件包括大致平行于并沿着有源区的相关带形成的隔离沟槽。 导电位线凹陷在每个隔离沟槽内，使得位线的最上表面凹陷在基底基板的最上表面之下。 位线接触带沿着位线带的垂直尺寸并且跨越基底的最上表面的水平尺寸将位线电耦合到有源区域。

公开(公告)号：US06780728B2

公开(公告)日：2004-08-24

申请号：US10177056

申请日：2002-06-21

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： H01L2176

CPC分类号： H01L21/76224 ,  H01L21/763

摘要： The invention includes a semiconductor construction. The construction includes a semiconductive material having a surface and an opening extending through the surface. An electrically insulative liner is along a periphery of the opening. A mass comprising one or more of silicon, germanium, metal, metal silicide and dopant is within a bottom portion of the opening, and only partially fills the opening. The mass has a top surface. An electrically insulative material is within the opening and over the top surface of the mass. The top surface of the mass is at least about 200 Angstroms beneath the surface of the semiconductive material. The invention also includes methods of forming semiconductor constructions.

摘要翻译： 本发明包括半导体结构。 该结构包括具有延伸穿过该表面的表面和开口的半导体材料。 电绝缘衬垫沿着开口的周边。 包括硅，锗，金属，金属硅化物和掺杂剂中的一种或多种的物质在开口的底部内，并且仅部分填充开口。 质量有顶面。 电绝缘材料位于该开口内部和该顶部表面之上。 该物体的顶表面在半导体材料表面下方至少约200埃。 本发明还包括形成半导体结构的方法。

公开(公告)号：US06756619B2

公开(公告)日：2004-06-29

申请号：US10229336

申请日：2002-08-26

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： H01L31113

CPC分类号： H01L27/10894 ,  H01L21/28044 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/1041 ,  H01L29/4916 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/78 ,  Y10S438/919 ,  Y10S438/975

摘要： The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. The transistors have gates that are wider than the underlying sub-regions. The invention also includes a semiconductor construction that has transistor constructions with insulative spacers along gate sidewalls. Each transistor construction is between a pair source/drain regions that extend beneath the spacers. A source/drain extension extends the source/drain region farther beneath the transistor constructions on only one side of each of the transistor constructions. The invention also includes methods of forming semiconductor constructions.

摘要翻译： 本发明包括具有一对沟道区的半导体结构，所述沟道区具有被铟掺杂并被硼包围的子区。 一对晶体管结构位于沟道区上方并由隔离区隔开。 晶体管具有比下面的子区域更宽的栅极。 本发明还包括半导体结构，其具有在栅极侧壁处具有绝缘间隔物的晶体管结构。 每个晶体管结构位于在间隔物下方延伸的一对源/漏区之间。 源极/漏极扩展器在仅在晶体管结构中的每一个的一侧上的晶体管结构之下延伸更远的源极/漏极区域。 本发明还包括形成半导体结构的方法。

公开(公告)号：US06734482B1

公开(公告)日：2004-05-11

申请号：US10295106

申请日：2002-11-15

申请人： Luan C. Tran ,  Mark Durcan ,  Howard C. Kirsch

发明人： Luan C. Tran ,  Mark Durcan ,  Howard C. Kirsch

IPC分类号： H01L27108

CPC分类号： H01L27/10885 ,  H01L27/10814 ,  H01L27/10888

摘要： A memory device such as a 6F2 memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermost surface of the base substrate. A bit line contact strap electrically couples the bit line to the active area both along a vertical dimension of the bit line strap and along a horizontal dimension across the uppermost surface of the base substrate.

摘要翻译： 诸如6F 2存储器件的存储器件包括大致平行于并沿着有源区的相关带形成的隔离沟槽。 导电位线凹陷在每个隔离沟槽内，使得位线的最上表面凹陷在基底基板的最上表面之下。 位线接触带沿着位线带的垂直尺寸并且跨越基底的最上表面的水平尺寸将位线电耦合到有源区域。

公开(公告)号：US06579751B2

公开(公告)日：2003-06-17

申请号：US09388856

申请日：1999-09-01

申请人： Luan C. Tran

发明人： Luan C. Tran

IPC分类号： H01L21337

CPC分类号： H01L21/823412 ,  H01L21/823425 ,  H01L27/1052 ,  H01L27/10894

摘要： Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo implants are conducted into the first type MOS transistors in less than all of the peripheral MOS transistors of the first type. In another embodiment, a plurality of n-type transistor devices are formed over a substrate and comprise memory array circuitry and peripheral circuitry. At least some of the individual peripheral circuitry n-type transistor devices are partially masked, and a halo implant is conducted for unmasked portions of the partially masked peripheral circuitry n-type transistor devices. In yet another embodiment, at least a portion of only one of the source and drain regions is masked, and at least a portion of the other of the source and drains regions is exposed for at least some of the peripheral circuitry n-type transistor devices. A halo implant is conducted relative to the exposed portions of the source and drain regions. In another embodiment, a common masking step is used and a halo implant is conducted of devices formed over a substrate comprising memory circuitry and peripheral circuitry sufficient to impart to at least three of the devices three different respective threshold voltages.

公开(公告)号：US06489226B2

公开(公告)日：2002-12-03

申请号：US09995373

申请日：2001-11-26

申请人： Pai-Hung Pan ,  Luan C. Tran ,  Tyler A. Lowrey

发明人： Pai-Hung Pan ,  Luan C. Tran ,  Tyler A. Lowrey

IPC分类号： H01L2144

CPC分类号： H01L27/10888 ,  H01L21/32051 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885

摘要： Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.

摘要翻译： 描述形成接触开口，存储器电路和动态随机存取存储器（DRAM）电路的方法。 在一个实施方案中，字线阵列和位线形成在衬底表面上并由中间绝缘层隔开。 位线的导电部分向外露出，并且在衬底和位线的暴露的导电部分上形成一层材料。 材料层的选定部分与中间层的部分一起被去除，足以使（a）暴露衬底表面的选定区域，并且（b）重新暴露位线的导电部分。 随后形成导电材料以将暴露的衬底区域与各个位线的相关联的导电部分电连接。