公开(公告)号：US20230206992A1

公开(公告)日：2023-06-29

申请号：US18083077

申请日：2022-12-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Junwyn A. Lacsao ,  Jeffrey S. McNeil ,  Violante Moschiano ,  Paing Z. Htet ,  Sead Zildzic ,  Eric N. Lee

IPC: G11C11/4091 ,  G11C11/4099 ,  G11C11/4093

CPC classification number: G11C11/4091 ,  G11C11/4093 ,  G11C11/4099

Abstract: Control logic in a memory device selects two or more blocks of a plurality of blocks to concurrently scan during a scan operation. The control logic can further cause a first voltage to be applied to a dummy word line of each block of the two or more blocks to selectively couple a string of memory cells in each block of the two or more blocks to a different sense amplifier of a set of sense amplifiers coupled with the plurality of blocks. The control logic can cause a second voltage to be applied to a selected word line of each block of the two or more blocks to read a bit stored at a respective memory cell of the string of memory cells in each block out to the set of sense amplifier.

公开(公告)号：US20230197163A1

公开(公告)日：2023-06-22

申请号：US18076488

申请日：2022-12-07

Applicant: Micron Technology, Inc.

Inventor： Jeffrey S. McNeil ,  Kishore Kumar Muchherla ,  Sead Zildzic ,  Akira Goda ,  Jonathan S. Parry ,  Violante Moschiano

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/28

CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/28

Abstract: A system includes a memory device including a memory array and control logic, operatively coupled with the memory array, to perform operations including receiving a set of commands to concurrently program a set of cells of the memory array with dummy data, the set of cells corresponding to a group of retired wordlines of the plurality of wordlines, in response to receiving the set of commands, obtaining the dummy data, and concurrently programming the set of cells with the dummy data by causing a ganged programming pulse to be applied to the set of cells.

公开(公告)号：US20230060440A1

公开(公告)日：2023-03-02

申请号：US17877411

申请日：2022-07-29

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Violante Moschiano ,  Akira Goda ,  Jeffrey S. McNeil ,  Eric N. Lee

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/406 ,  G11C11/4072

Abstract: Control logic in a memory device determines to initiate a string read operation on a first memory string of a plurality of memory strings in a block of a memory array of the memory device, the block comprising a plurality of wordlines, wherein each of the plurality of memory strings comprises a plurality of memory cells associated with the plurality of wordlines, and wherein the first memory string is designated as a sacrificial string. The control logic further causes a read voltage to be applied to each of the plurality of wordlines of the memory array concurrently and senses a level of current flowing through the first memory string designated as the sacrificial string while the read voltage is applied to each of the plurality of wordline. In addition, the control logic identifies, based on the level of current flowing through the first memory string designated as the sacrificial string, whether a threshold level of read disturb has occurred on the block.

公开(公告)号：US11069408B2

公开(公告)日：2021-07-20

申请号：US16861435

申请日：2020-04-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeffrey S. McNeil

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/26 ,  G11C16/14 ,  G11C16/10

Abstract: Apparatus configured to perform an access operation on a memory cell of an array of memory cells, discharge a control gate of a first field-effect transistor after performing the access operation, discharge a control gate of a second field-effect transistor connected in series between the first field-effect transistor and the memory cell after discharging the control gate of the first field-effect transistor, and discharge a control gate of the memory cell after discharging the control gate of the second field-effect transistor.