公开(公告)号：US11715547B2

公开(公告)日：2023-08-01

申请号：US17946207

申请日：2022-09-16

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Violante Moschiano ,  Sead Zildzic ,  Junwyn A. Lacsao ,  Paing Z. Htet

IPC: G11C29/42 ,  G11C29/44 ,  G11C11/4074 ,  G11C11/408 ,  G11C29/50

CPC classification number: G11C29/42 ,  G11C11/4074 ,  G11C11/4085 ,  G11C29/44 ,  G11C29/50004

Abstract: A system includes a memory array of sub-blocks, each sub-block including groups of memory cells, and a processing device. The processing device causes a first wordline to be programmed through the sub-blocks with a mask by causing to be programmed, to a first voltage level: a first group of memory cells of a first sub-block; and a second group of memory cells of a second sub-block. The processing device further scans a second wordline that has been programmed and is coupled to the first wordline, scanning includes: causing a custom wordline voltage to be applied to the second wordline, the custom wordline voltage to select groups of memory cells corresponding to those of the first wordline programmed to the first voltage level; concurrently reading data from the selected groups of memory cells of the second wordline; and performing, using the data, an error check of the second wordline.

公开(公告)号：US20230307053A1

公开(公告)日：2023-09-28

申请号：US18119997

申请日：2023-03-10

Applicant: Micron Technology, Inc.

Inventor： Paing Z. Htet ,  Akira Goda ,  Eric N. Lee ,  Jeffrey S. McNeil ,  Junwyn A. Lacsao ,  Kishore Kumar Muchherla ,  Sead Zildzic ,  Violante Moschiano

IPC: G11C16/08 ,  G11C16/26 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C16/26 ,  G11C16/102 ,  G11C16/0433

Abstract: A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.

公开(公告)号：US20250140317A1

公开(公告)日：2025-05-01

申请号：US19008498

申请日：2025-01-02

Applicant: Micron Technology, Inc.

Inventor： Paing Z. Htet ,  Akira Goda ,  Eric N. Lee ,  Jeffrey S. McNeil ,  Junwyn A. Lacsao ,  Kishore Kumar Muchherla ,  Sead Zildzic ,  Violante Moschiano

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.

公开(公告)号：US12217799B2

公开(公告)日：2025-02-04

申请号：US18119997

申请日：2023-03-10

Applicant: Micron Technology, Inc.

Inventor： Paing Z. Htet ,  Akira Goda ,  Eric N. Lee ,  Jeffrey S. McNeil ,  Junwyn A. Lacsao ,  Kishore Kumar Muchherla ,  Sead Zildzic ,  Violante Moschiano

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.

公开(公告)号：US20230206992A1

公开(公告)日：2023-06-29

申请号：US18083077

申请日：2022-12-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Junwyn A. Lacsao ,  Jeffrey S. McNeil ,  Violante Moschiano ,  Paing Z. Htet ,  Sead Zildzic ,  Eric N. Lee

IPC: G11C11/4091 ,  G11C11/4099 ,  G11C11/4093

CPC classification number: G11C11/4091 ,  G11C11/4093 ,  G11C11/4099

Abstract: Control logic in a memory device selects two or more blocks of a plurality of blocks to concurrently scan during a scan operation. The control logic can further cause a first voltage to be applied to a dummy word line of each block of the two or more blocks to selectively couple a string of memory cells in each block of the two or more blocks to a different sense amplifier of a set of sense amplifiers coupled with the plurality of blocks. The control logic can cause a second voltage to be applied to a selected word line of each block of the two or more blocks to read a bit stored at a respective memory cell of the string of memory cells in each block out to the set of sense amplifier.

公开(公告)号：US20230012644A1

公开(公告)日：2023-01-19

申请号：US17946207

申请日：2022-09-16

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Violante Moschiano ,  Sead Zildzic ,  Junwyn A. Lacsao ,  Paing Z. Htet

IPC: G11C29/42 ,  G11C29/44 ,  G11C11/4074 ,  G11C11/408 ,  G11C29/50

Abstract: A system includes a memory array of sub-blocks, each sub-block including groups of memory cells, and a processing device. The processing device causes a first wordline to be programmed through the sub-blocks with a mask by causing to be programmed, to a first voltage level: a first group of memory cells of a first sub-block; and a second group of memory cells of a second sub-block. The processing device further scans a second wordline that has been programmed and is coupled to the first wordline, scanning includes: causing a custom wordline voltage to be applied to the second wordline, the custom wordline voltage to select groups of memory cells corresponding to those of the first wordline programmed to the first voltage level; concurrently reading data from the selected groups of memory cells of the second wordline; and performing, using the data, an error check of the second wordline.

公开(公告)号：US11475969B2

公开(公告)日：2022-10-18

申请号：US17247633

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Violante Moschiano ,  Sead Zildzic ,  Junwyn A. Lacsao ,  Paing Z. Htet

IPC: G11C29/42 ,  G11C29/44 ,  G11C11/4074 ,  G11C11/408 ,  G11C29/50

Abstract: A system includes a memory array with sub-blocks, each sub-block having groups of memory cells. A processing device, operatively coupled with the memory array, is to perform operations including performing, after a wordline is programmed through the sub-blocks, scanning of the wordline. The scanning includes selecting, to sample first data of the wordline, a first group of the groups of memory cells of a first sub-block of the sub-blocks; selecting, to sample second data of the wordline, a second group of the groups of memory cells of a second sub-block of the sub-blocks; concurrently reading the first data from the first group and the second data from the second group of the groups of memory cells; and performing an error check of the wordline using the first data and the second data.

公开(公告)号：US20220199184A1

公开(公告)日：2022-06-23

申请号：US17247633

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Violante Moschiano ,  Sead Zildzic ,  Junwyn A. Lacsao ,  Paing Z. Htet

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/50 ,  G11C11/408 ,  G11C11/4074

Abstract: A system includes a memory array with sub-blocks, each sub-block having groups of memory cells. A processing device, operatively coupled with the memory array, is to perform operations including performing, after a wordline is programmed through the sub-blocks, scanning of the wordline. The scanning includes selecting, to sample first data of the wordline, a first group of the groups of memory cells of a first sub-block of the sub-blocks; selecting, to sample second data of the wordline, a second group of the groups of memory cells of a second sub-block of the sub-blocks; concurrently reading the first data from the first group and the second data from the second group of the groups of memory cells; and performing an error check of the wordline using the first data and the second data.