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公开(公告)号：US20250140317A1
公开(公告)日：2025-05-01
申请号：US19008498
申请日：2025-01-02
Applicant: Micron Technology, Inc.
Inventor： Paing Z. Htet , Akira Goda , Eric N. Lee , Jeffrey S. McNeil , Junwyn A. Lacsao , Kishore Kumar Muchherla , Sead Zildzic , Violante Moschiano
Abstract: A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.
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公开(公告)号：US20240087655A1
公开(公告)日：2024-03-14
申请号：US17942977
申请日：2022-09-12
Applicant: Micron Technology, Inc.
Inventor： Nagendra Prasad Ganesh Rao , Paing Z. Htet , Sead Zildzic, JR. , Thomas Fiala , Jian Huang , Zhenming Zhou
Abstract: A system can include a memory device containing blocks made up of wordlines respectively connected to sets of memory cells, and a processing device, operatively coupled with the memory device to perform operations including responsive to receiving a read request that specifies a block, determining a value of a metric reflective of a number of programmed wordlines of the block. The operations can also include responsive to determining, based on the value of the metric, that the block is in a partially programmed state, identifying a read voltage offset corresponding to the value of the metric, and performing, using the read voltage offset, a read operation responsive to the read request.
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公开(公告)号：US11715547B2
公开(公告)日：2023-08-01
申请号：US17946207
申请日：2022-09-16
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Violante Moschiano , Sead Zildzic , Junwyn A. Lacsao , Paing Z. Htet
IPC: G11C29/42 , G11C29/44 , G11C11/4074 , G11C11/408 , G11C29/50
CPC classification number: G11C29/42 , G11C11/4074 , G11C11/4085 , G11C29/44 , G11C29/50004
Abstract: A system includes a memory array of sub-blocks, each sub-block including groups of memory cells, and a processing device. The processing device causes a first wordline to be programmed through the sub-blocks with a mask by causing to be programmed, to a first voltage level: a first group of memory cells of a first sub-block; and a second group of memory cells of a second sub-block. The processing device further scans a second wordline that has been programmed and is coupled to the first wordline, scanning includes: causing a custom wordline voltage to be applied to the second wordline, the custom wordline voltage to select groups of memory cells corresponding to those of the first wordline programmed to the first voltage level; concurrently reading data from the selected groups of memory cells of the second wordline; and performing, using the data, an error check of the second wordline.
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公开(公告)号：US20250124987A1
公开(公告)日：2025-04-17
申请号：US18990013
申请日：2024-12-20
Applicant: Micron Technology, Inc.
Inventor： Nagendra Prasad Ganesh Rao , Paing Z. Htet , Sead Zildzic, JR. , Thomas Fiala , Jian Huang , Zhenming Zhou
Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations, including: determining a read voltage offset corresponding to a value of a metric reflective of a programmed state of a set of memory cells of the memory device; and performing, using the read voltage offset, a memory access operation with respect to the set of memory cells.
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公开(公告)号：US12217799B2
公开(公告)日：2025-02-04
申请号：US18119997
申请日：2023-03-10
Applicant: Micron Technology, Inc.
Inventor： Paing Z. Htet , Akira Goda , Eric N. Lee , Jeffrey S. McNeil , Junwyn A. Lacsao , Kishore Kumar Muchherla , Sead Zildzic , Violante Moschiano
Abstract: A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.
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Patent Agency Ranking
公开(公告)号：US20230206992A1
公开(公告)日：2023-06-29
申请号：US18083077
申请日：2022-12-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Kishore Kumar Muchherla , Junwyn A. Lacsao , Jeffrey S. McNeil , Violante Moschiano , Paing Z. Htet , Sead Zildzic , Eric N. Lee
IPC: G11C11/4091 , G11C11/4099 , G11C11/4093
CPC classification number: G11C11/4091 , G11C11/4093 , G11C11/4099
Abstract: Control logic in a memory device selects two or more blocks of a plurality of blocks to concurrently scan during a scan operation. The control logic can further cause a first voltage to be applied to a dummy word line of each block of the two or more blocks to selectively couple a string of memory cells in each block of the two or more blocks to a different sense amplifier of a set of sense amplifiers coupled with the plurality of blocks. The control logic can cause a second voltage to be applied to a selected word line of each block of the two or more blocks to read a bit stored at a respective memory cell of the string of memory cells in each block out to the set of sense amplifier.
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公开(公告)号：US12272408B2
公开(公告)日：2025-04-08
申请号：US18138489
申请日：2023-04-24
Applicant: Micron Technology, Inc.
Inventor： Nagendra Prasad Ganesh Rao , Paing Z. Htet , Sead Zildzic, Jr. , Thomas Fiala
Abstract: A memory device includes a memory array having a plurality of wordlines coupled with respective memory cells of the memory array. Control logic is operatively coupled with the memory array, the control logic to perform operations including: determining, prior to performing a read operation at one or more strings of the respective memory cells, a number of wordlines that are associated with memory cells that have been programmed; adjusting, based on the number of wordlines, a read level voltage for a selected wordline of the one or more strings that is to be read during the read operation; and causing, during the read operation, the adjusted read level voltage to be applied to the selected wordline.
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公开(公告)号：US20230368845A1
公开(公告)日：2023-11-16
申请号：US18138489
申请日：2023-04-24
Applicant: Micron Technology, Inc.
Inventor： Nagendra Prasad Ganesh Rao , Paing Z. Htet , Sead Zildzic, JR. , Thomas Fiala
CPC classification number: G11C16/26 , G11C16/08 , G11C16/102
Abstract: A memory device includes a memory array having a plurality of wordlines coupled with respective memory cells of the memory array. Control logic is operatively coupled with the memory array, the control logic to perform operations including: determining, prior to performing a read operation at one or more strings of the respective memory cells, a number of wordlines that are associated with memory cells that have been programmed; adjusting, based on the number of wordlines, a read level voltage for a selected wordline of the one or more strings that is to be read during the read operation; and causing, during the read operation, the adjusted read level voltage to be applied to the selected wordline.
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公开(公告)号：US20230307053A1
公开(公告)日：2023-09-28
申请号：US18119997
申请日：2023-03-10
Applicant: Micron Technology, Inc.
Inventor： Paing Z. Htet , Akira Goda , Eric N. Lee , Jeffrey S. McNeil , Junwyn A. Lacsao , Kishore Kumar Muchherla , Sead Zildzic , Violante Moschiano
CPC classification number: G11C16/08 , G11C16/26 , G11C16/102 , G11C16/0433
Abstract: A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.
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公开(公告)号：US12224017B2
公开(公告)日：2025-02-11
申请号：US17942977
申请日：2022-09-12
Applicant: Micron Technology, Inc.
Inventor： Nagendra Prasad Ganesh Rao , Paing Z. Htet , Sead Zildzic, Jr. , Thomas Fiala , Jian Huang , Zhenming Zhou
Abstract: A system can include a memory device containing blocks made up of wordlines respectively connected to sets of memory cells, and a processing device, operatively coupled with the memory device to perform operations including responsive to receiving a read request that specifies a block, determining a value of a metric reflective of a number of programmed wordlines of the block. The operations can also include responsive to determining, based on the value of the metric, that the block is in a partially programmed state, identifying a read voltage offset corresponding to the value of the metric, and performing, using the read voltage offset, a read operation responsive to the read request.
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