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    Timing control of voltage supply during polarity transition
    61.
    发明授权
    Timing control of voltage supply during polarity transition 有权

    公开(公告)号：US11183237B2

    公开(公告)日：2021-11-23

    申请号：US17037495

    申请日：2020-09-29

    Applicant: Micron Technology, Inc.

    Inventor： Mingdong Cui ,  Nathan Joseph Sirocka ,  Byung Sick Moon ,  Jeffrey Edward Koelling

    IPC: G11C13/00 ,  H03K19/20

    Abstract: A timing control circuit in an integrated circuit memory device. The circuit has an input line, a first output line and a second output line. The input line configured to receive a control signal for the timing control circuit to generate, a first selection input on the first output line and a second selection input on the second output line. In response to the control signal transitioning from a first state to a second state, the first selection input completes a first transition before the second selection input starts a second transition (e.g., for selection between 0V and −4.5V); and in response to the control signal transitioning from the second state to the first state, the second selection input completes a third transition before the first selection input starts fourth transition (e.g., for selection between 5V and 1.2V). The sequential transitions avoid simultaneous selection of 5V and −4.5V.

    REFRESH OPERATION OF A MEMORY CELL
    62.
    发明申请
    REFRESH OPERATION OF A MEMORY CELL 有权

    公开(公告)号：US20210358546A1

    公开(公告)日：2021-11-18

    申请号：US15931131

    申请日：2020-05-13

    Applicant: Micron Technology, Inc.

    Inventor： Joemar Sinipete ,  John Christopher Sancon ,  Mingdong Cui

    IPC: G11C13/00

    Abstract: Methods, systems, and devices for a refresh operation of a memory cell are described. A memory device may include a plurality of rows of memory cells. Each row of memory cells may undergo a quantity of access operations (e.g., read operations, write operations). During a read operation, a logic state of one or more memory cells may be determined by applying a read pulse having a first polarity. Based on the one or more memory cells storing a particular logic state (e.g., a first logic state), a refresh operation may be performed. During a refresh operation, a refresh pulse having a second polarity (e.g., a different polarity than the first polarity) may be applied to the one or more memory cells.

    Voltage Drivers with Reduced Power Consumption during Polarity Transition
    63.
    发明申请
    Voltage Drivers with Reduced Power Consumption during Polarity Transition 有权

    公开(公告)号：US20210343340A1

    公开(公告)日：2021-11-04

    申请号：US17375441

    申请日：2021-07-14

    Applicant: Micron Technology, Inc.

    Inventor： Mingdong Cui ,  Nathan Joseph Sirocka ,  Hari Giduturi

    IPC: G11C13/00

    Abstract: An integrated circuit memory device having: a memory cell; and a voltage driver of depletion type connected to the memory cell. In a first polarity, the voltage driver is powered by a negative voltage relative to ground to drive a negative selection voltage or a first de-selection voltage; In a second polarity, the voltage driver is powered by a positive voltage relative to ground to drive a positive selection voltage or a second de-selection voltage. The voltage driver is configured to transition between the first polarity and the second polarity. During the transition, the voltage driver is configured to have a control voltage swing for outputting de-selection voltages smaller than a control voltage swing for output selection voltages.

    Mux Decoder with Polarity Transition Capability
    64.
    发明申请
    Mux Decoder with Polarity Transition Capability 有权

    公开(公告)号：US20210312981A1

    公开(公告)日：2021-10-07

    申请号：US17350422

    申请日：2021-06-17

    Applicant: Micron Technology, Inc.

    Inventor： Nathan Joseph Sirocka ,  Mingdong Cui ,  Jeffrey Edward Koelling

    IPC: G11C13/00

    Abstract: A decoder in an integrated circuit memory device having: a positive section having a first input line; a negative section having a second input line; and an output line connected from both the positive section and the negative section to a voltage driver connected to a memory cell. The positive section and the negative sections are controlled by a polarity control signal. When the polarity control signal indicates positive polarity, the positive section drives the output line according to signals received in the first input line; and when the polarity control signal indicates negative polarity, the negative section drives the output line according to signals received in the second input line.

    Two-stage signaling for voltage driver coordination in integrated circuit memory devices
    65.
    发明授权
    Two-stage signaling for voltage driver coordination in integrated circuit memory devices 有权

    公开(公告)号：US11133056B2

    公开(公告)日：2021-09-28

    申请号：US17037497

    申请日：2020-09-29

    Applicant: Micron Technology, Inc.

    Inventor： Nathan Joseph Sirocka ,  Mingdong Cui

    IPC: G11C11/41 ,  G11C11/413 ,  G11C11/4074 ,  G11C29/50 ,  G11C11/408 ,  G11C11/4094 ,  G11C5/14

    Abstract: An integrated circuit memory device, having: memory cells; a circuit patch configured on an integrated circuit die; a plurality of neighboring patches configured on the integrated circuit die; first connections from the circuit patch to the neighboring patches respectively; a plurality of surrounding patches configured on the integrated circuit die; and second connections from the neighboring patches to the surrounding patches. In determining whether or not to apply an offset voltage to be driven by the neighboring patches and the surrounding patches on non-selected memory cells, to at least partially offset a voltage increase applied by the circuit patch on one or more selected memory cells, the circuit patch communicates with the neighboring patches through the first connections, and communicates with the surrounding patches through the first connections, the neighboring patches, and the second connections.

    Voltage drivers with reduced power consumption during polarity transition
    66.
    发明授权
    Voltage drivers with reduced power consumption during polarity transition 有权

    公开(公告)号：US11087838B2

    公开(公告)日：2021-08-10

    申请号：US16660594

    申请日：2019-10-22

    Applicant: Micron Technology, Inc.

    Inventor： Mingdong Cui ,  Nathan Joseph Sirocka ,  Hari Giduturi

    IPC: G11C13/00

    Abstract: An integrated circuit memory device having: a memory cell; and a voltage driver of depletion type connected to the memory cell. In a first polarity, the voltage driver is powered by a negative voltage relative to ground to drive a negative selection voltage or a first de-selection voltage; In a second polarity, the voltage driver is powered by a positive voltage relative to ground to drive a positive selection voltage or a second de-selection voltage. The voltage driver is configured to transition between the first polarity and the second polarity. During the transition, the voltage driver is configured to have a control voltage swing for outputting de-selection voltages smaller than a control voltage swing for output selection voltages.

    Mux Decoder with Polarity Transition Capability
    67.
    发明申请
    Mux Decoder with Polarity Transition Capability 有权

    公开(公告)号：US20210134363A1

    公开(公告)日：2021-05-06

    申请号：US16668549

    申请日：2019-10-30

    Applicant: Micron Technology, Inc.

    Inventor： Nathan Joseph Sirocka ,  Mingdong Cui ,  Jeffrey Edward Koelling

    IPC: G11C13/00

    Abstract: A decoder in an integrated circuit memory device having: a positive section having a first input line; a negative section having a second input line; and an output line connected from both the positive section and the negative section to a voltage driver connected to a memory cell. The positive section and the negative sections are controlled by a polarity control signal. When the polarity control signal indicates positive polarity, the positive section drives the output line according to signals received in the first input line; and when the polarity control signal indicates negative polarity, the negative section drives the output line according to signals received in the second input line.

    TECHNIQUES FOR APPLYING MULTIPLE VOLTAGE PULSES TO SELECT A MEMORY CELL
    68.
    发明申请
    TECHNIQUES FOR APPLYING MULTIPLE VOLTAGE PULSES TO SELECT A MEMORY CELL 有权

    公开(公告)号：US20210005254A1

    公开(公告)日：2021-01-07

    申请号：US16460863

    申请日：2019-07-02

    Applicant: Micron Technology, Inc.

    Inventor： Josephine T. Hamada ,  Mingdong Cui ,  Joseph M. McCrate ,  Karthik Sarpatwari ,  Jessica Chen

    IPC: G11C13/00 ,  H01L45/00 ,  G11C5/14

    Abstract: Methods, systems, and devices for memory cell selection to enable a memory device to select a targeted memory cell during a write operation are described. The memory device may apply a first pulse to a selected bit line of the targeted memory cell while applying a voltage to deselected word lines to prevent current leakage. If the targeted memory is not selected after the first pulse, the memory device may apply a second pulse to the selected bit line while applying a voltage to the deselected word lines. If the targeted memory cell is not selected following the second pulse, the memory device may apply a third pulse to the selected bit line while applying the voltage to the deselected word lines. The memory device may detect a snapback event after any of the pulses if the targeted memory cell is selected.

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