公开(公告)号：US20240098970A1

公开(公告)日：2024-03-21

申请号：US17946925

申请日：2022-09-16

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Si-Woo Lee ,  David K. Hwang ,  Yoshitaka Nakamura ,  Yuanzhi Ma ,  Glen H. Walters

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/10882

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source drain regions separated by silicon (Si) channel regions. A digit line having a global digit line (GDL) contact is formed in a trench adjacent to the first source/drain regions. In one example, the digit line is electrically isolated from a neighboring digit line at the bottom of the trench. In another example, the digit line is formed continuously along a bottom surface of trench to form shared digit lines between horizontal access devices, in two separate arrays, on opposing second vertical surfaces. The memory cells have horizontally oriented storage nodes coupled to the second source/drain regions and vertical digit lines coupled to the first source/drain regions.

公开(公告)号：US20240074141A1

公开(公告)日：2024-02-29

申请号：US17895017

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： Yoshitaka Nakamura ,  Yuanzhi Ma ,  Scott E. Sills ,  Si-Woo Lee ,  David K. Hwang

IPC: H01L27/108 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/10805 ,  H01L27/1085 ,  H01L27/10873 ,  H01L29/66742 ,  H01L29/78696

Abstract: Methods and devices for a lateral three-dimensional memory device, are described herein. One method includes forming a thin film transistor including a first thermal process having a first range of temperatures, forming a capacitor bottom electrode of a capacitor structure including a second thermal process having a second range of temperature, wherein a maximum temperature in the second range of temperatures is less than a maximum temperature in the first range of temperatures, forming a CMOS structure including a third thermal process having a third range of temperatures, wherein a maximum temperature in the third range of temperatures is less than a maximum temperature in the second range of temperatures, and forming at least one other part of the capacitor structure.

公开(公告)号：US20240064966A1

公开(公告)日：2024-02-22

申请号：US17891790

申请日：2022-08-19

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Litao Yang ,  Haitao Liu ,  Si-Woo Lee

IPC: H01L27/108 ,  G11C11/22

CPC classification number: H01L27/10826 ,  G11C11/221 ,  H01L27/10882

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells. The vertically stacked memory cells have horizontally oriented access devices having a first source/drain region, a channel region, and a second source drain and horizontally oriented storage nodes that are vertically separated from the access devices. Horizontally oriented access lines are coupled to gates, separated from the respective channel regions by gate dielectrics, and vertically oriented digit lines are coupled to respective first source/drain regions. The horizontally oriented storage nodes each have a first electrode coupled to the second source/drain regions of the access devices and each first electrode opposes two different sides of the horizontal access devices including an electrical contact with a vertical side of the second source/drain regions.

公开(公告)号：US11869803B2

公开(公告)日：2024-01-09

申请号：US17749282

申请日：2022-05-20

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Byung Yoon Kim

IPC: H01L21/762 ,  H01L21/02 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L21/76251 ,  H01L21/02532 ,  H01L21/02598 ,  H01L25/18 ,  H01L25/50 ,  H01L21/02381

Abstract: Systems, methods, and apparatus are provided for single crystalline silicon stack formation and bonding to a complimentary metal oxide semiconductor (CMOS) wafer for formation of vertical three dimensional (3D) memory. An example method for forming arrays of vertically stacked layers for formation of memory cells includes providing a silicon substrate, forming a layer of single crystal silicon germanium onto a surface of the substrate, epitaxially growing the silicon germanium to form a thicker silicon germanium layer, forming a layer of single crystal silicon onto a surface of the silicon germanium, epitaxially growing the silicon germanium to form a thicker silicon layer, and forming, in repeating iterations, layers of silicon germanium and silicon to form a vertical stack of alternating silicon and silicon germanium layers.

公开(公告)号：US20230397402A1

公开(公告)日：2023-12-07

申请号：US18054316

申请日：2022-11-10

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/10897 ,  H01L27/1085 ,  H01L27/10873 ,  H01L27/10885

Abstract: A microelectronic device comprises vertical stacks of memory cells, each of the vertical stacks of memory cells comprising a vertical stack of access devices, a vertical stack of capacitors horizontally neighboring the vertical stack of access devices, and a conductive pillar structure in contact with the vertical stack of access devices. The microelectronic device further comprises transistor structures vertically overlying the vertical stacks of memory cells and comprising semiconductive material, and a protective liner material horizontally intervening between the semiconductive material and the conductive pillar structure of each of the vertical stacks of memory cells. Related methods are also described.

公开(公告)号：US20230397391A1

公开(公告)日：2023-12-07

申请号：US17888467

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Scott E. Sills ,  David K. Hwang ,  Yoshitaka Nakamura ,  Yuanzhi Ma ,  Glen H. Walters

IPC: H01L27/108

CPC classification number: H01L27/10873 ,  H01L27/10805 ,  H01L27/1085 ,  H01L27/10885

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. A support structure is provided to the epitaxially grown, single crystalline Si. Horizontally oriented access lines connect to gates opposing the channel regions formed fully around every surface of the channel region as gate all around (GAA) structures separated from the channel regions by gate dielectrics. The memory cells have horizontally oriented storage nodes coupled to the second source/drain regions and vertical digit lines coupled to the first source/drain regions.

公开(公告)号：US11563008B2

公开(公告)日：2023-01-24

申请号：US17194859

申请日：2021-03-08

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang ,  Vinay Nair ,  Devesh Dadhich Shreeram ,  Ashwin Panday ,  Kangle Li ,  Zhiqiang Xie ,  Silvia Borsari ,  Mohd Kamran Akhtar ,  Si-Woo Lee

IPC: H01L27/108

Abstract: Some embodiments include an integrated assembly having digit-line-contact-regions between pairs of capacitor-contact-regions. The capacitor-contact-regions are arranged with six adjacent capacitor-contact-regions in a substantially rectangular configuration. Conductive plugs are coupled with the capacitor-contact-regions. Conductive redistribution material is coupled with the conductive plugs. Upper surfaces of the conductive redistribution material are arranged in a substantially hexagonal-close-packed configuration. Digit lines are over the digit-line-contact-regions. Insulative regions are between the digit lines and the conductive plugs. The insulative regions contain voids and/or low-k dielectric material. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

公开(公告)号：US20220352171A1

公开(公告)日：2022-11-03

申请号：US17867628

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Sangmin Hwang

IPC: H01L27/108

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines, and vertically oriented digit lines having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region, horizontal oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region of the horizontally oriented access devices. The vertically oriented digit lines are formed in direct electrical contact with the first source/drain regions of the horizontally oriented access devices. A vertically oriented body contact line is integrated to form the body contact to the body region of the horizontally oriented access device and separate from the first source/drain region and the vertically oriented digit lines by a dielectric.

公开(公告)号：US11476251B2

公开(公告)日：2022-10-18

申请号：US16986466

申请日：2020-08-06

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  John A. Smythe, III ,  Si-Woo Lee ,  Gurtej S. Sandhu ,  Armin Saeedi Vahdat

IPC: H01L27/108 ,  H01L29/786 ,  H01L29/78 ,  H01L27/11578 ,  H01L27/11597

Abstract: Systems, methods and apparatus are provided for a three-node access device in vertical three dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial material in repeating iterations to form a vertical stack. An etchant process is used to form a first vertical opening exposing vertical sidewalls in the vertical stack adjacent a first region. The first region is selectively etched to form a first horizontal opening removing the sacrificial material a first horizontal distance back from the first vertical opening. A first source/drain material, a replacement channel material having backchannel passivation, and a second source/drain material are deposited in the first horizontal opening to form the three-node access device for a memory cell among the arrays of vertically stacked memory cells.

公开(公告)号：US11469236B2

公开(公告)日：2022-10-11

申请号：US16732454

申请日：2020-01-02

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee

IPC: H01L27/10 ,  H01L27/108 ,  H01L21/768 ,  H01L23/522

Abstract: Integrated circuitry comprises a first conductive line buried within semiconductive material of a substrate. The first conductive line comprises conductively-doped semiconductor material directly above and directly against metal material in a vertical cross-section. A second conductive line is above the semiconductive material and is laterally-spaced from the first conductive line in the vertical cross-section. The second conductive line comprises metal material in the vertical cross-section. Insulative material is directly above the first and second conductive lines. A first conductive via extends through the insulative material and through the conductively-doped semiconductor material to the metal material of the first conductive line. A second conductive via extends through the insulative material to the metal material of the second conductive line. Other embodiments and aspects, including method, are disclosed.