公开(公告)号：US20240274223A1

公开(公告)日：2024-08-15

申请号：US18430406

申请日：2024-02-01

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G11C29/00

CPC classification number: G11C29/76 ,  G11C29/789

Abstract: A bank of a memory device may be divided into column planes. Each column plane may be associated with column selects. In some examples, a portion of a column plane associated with one column select may be used to store metadata associated with data of the remaining column selects. In some examples, the metadata may be mapped to the data based on a portion of a column address. In some examples, whether the memory device provides metadata responsive to a column address may be based on a value stored in a mode register. In some examples, the portion of the column plane associated with the one column select associated with metadata may also store error correction code data associated with the data of the remaining column selects.

公开(公告)号：US20240273014A1

公开(公告)日：2024-08-15

申请号：US18430381

申请日：2024-02-01

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G06F12/02 ,  G06F11/10

CPC classification number: G06F12/0223 ,  G06F11/1044

Abstract: A bank of a memory device may be divided into column planes. Each column plane may be associated with column selects. In some examples, a portion of a column plane associated with one column select may be used to store metadata associated with data of the remaining column selects. In some examples, the metadata may be mapped to the data based on a portion of a column address. In some examples, whether the memory device provides metadata responsive to a column address may be based on a value stored in a mode register. In some examples, the portion of the column plane associated with the one column select associated with metadata may also store error correction code data associated with the data of the remaining column selects.

公开(公告)号：US20240161855A1

公开(公告)日：2024-05-16

申请号：US18504215

申请日：2023-11-08

Applicant: Micron Technology, Inc.

Inventor： Scott E. Smith ,  Sujeet Ayyapureddi

IPC: G11C29/42

CPC classification number: G11C29/42

Abstract: Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

公开(公告)号：US20240160527A1

公开(公告)日：2024-05-16

申请号：US18504316

申请日：2023-11-08

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi ,  Scott E. Smith

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/1016 ,  G06F11/1024

Abstract: Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.

公开(公告)号：US20240038291A1

公开(公告)日：2024-02-01

申请号：US17973726

申请日：2022-10-26

Applicant: Micron Technology, Inc.

Inventor： Edmund J. Gieske ,  Sujeet Ayyapureddi ,  Niccolò Izzo

IPC: G11C11/4078 ,  G11C11/4096 ,  G11C11/4076

CPC classification number: G11C11/4078 ,  G11C11/4096 ,  G11C11/4076

Abstract: An apparatus can include a number of memory devices and a controller coupled to one or more of the number of memory devices. The controller can be configured to determine whether a quantity of row activations directed to a row of the memory devices exceeds a row hammer criterion. The controller can be configured to select, responsive to determining that the row hammer criterion is met, a row hammer mitigation response from a plurality of row hammer mitigation responses available for initiation. The controller can be configured to initiate the selected row hammer mitigation response.

公开(公告)号：US20240036762A1

公开(公告)日：2024-02-01

申请号：US18227216

申请日：2023-07-27

Applicant: Micron Technology, Inc.

Inventor： Edmund J. Gieske ,  Cagdas Dirik ,  Elliott C. Cooper-Balis ,  Robert M. Walker ,  Amitava Majumdar ,  Sujeet Ayyapureddi ,  Yang Lu ,  Ameen D. Akel ,  Niccolò Izzo ,  Danilo Caraccio ,  Markus H. Geiger

IPC: G06F3/06 ,  G06F12/0802

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0673 ,  G06F12/0802 ,  G06F2212/60

Abstract: Systems, apparatuses, and methods related to bloom filter implementation into a controller are described. A memory device is coupled to a memory controller. The memory controller is configured to implement a counting bloom filter, increment the counting bloom filter in response to a row activate command of the memory device, determine whether a value of the counting bloom filter exceeds a threshold value, and perform an action in response to the value exceeding the threshold value.

公开(公告)号：US11579971B2

公开(公告)日：2023-02-14

申请号：US17375957

申请日：2021-07-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi

IPC: G06F11/00 ,  G06F11/10 ,  G11C11/406 ,  G11C11/4063

Abstract: A memory performs a sequence of ECS operations to read a codeword, detect and correct any errors, and write the corrected codeword back to the memory array. An ECS circuit counts errors which are detected, and sets a value of one or more ECS registers in a mode register if the count exceeds a threshold filter at the end of the ECS cycle. The memory also includes a forced ECS readout circuit, which responsive to a command, for example from a controller, sets the value(s) in the ECS register(s).

公开(公告)号：US20230010619A1

公开(公告)日：2023-01-12

申请号：US17932206

申请日：2022-09-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi ,  Donald M. Morgan

IPC: G11C11/4078 ,  G11C11/408 ,  G11C11/406

Abstract: Apparatuses, systems, and methods for dynamically allocated aggressor detection. A memory may include an aggressor address storage structure which tracks access patterns to row addresses and their associated bank addresses. These may be used to determine if a row and bank address received as part of an access operation are an aggressor row and bank address. The aggressor row address may be used to generate a refresh address for a bank identified by the aggressor bank address. Since the aggressor storage structure tracks both row and bank addresses, its storage space may be dynamically allocated between banks based on access patterns to those banks.

公开(公告)号：US20220399902A1

公开(公告)日：2022-12-15

申请号：US17348654

申请日：2021-06-15

Applicant: Micron Technology, Inc.

Inventor： Markus H. Geiger ,  Matthew A. Prather ,  Sujeet Ayyapureddi ,  C. Omar Benitez ,  Dennis Montierth

IPC: H03M13/09 ,  G06F11/10

Abstract: Apparatuses, systems, and methods for multi-bit error detection. A memory device may store data bits and parity bits in a memory array. An error correction code (ECC) circuit may generate syndrome bits based on the data and parity bits and use the syndrome bits to correct up to a single bit error in the data and parity bits. A multi-bit error (MBE) detection circuit may detect an MBE in the data and parity based on at least one of the syndrome bits or the parity bits. For example, the MBE detection circuit may determine if the syndrome bits have a mapped or unmapped state and/or may compare the parity bits, data bits, and an additional parity bit to determine if there is an MBE. When an MBE is detected an MBE signal is activated. In some embodiments, an MBE flag may be set based on the MBE signal being active.

公开(公告)号：US20220230672A1

公开(公告)日：2022-07-21

申请号：US17153555

申请日：2021-01-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi ,  Donald M. Morgan

IPC: G11C11/4078 ,  G11C11/406 ,  G11C11/408

Abstract: Apparatuses, systems, and methods for dynamically allocated aggressor detection. A memory may include an aggressor address storage structure which tracks access patterns to row addresses and their associated bank addresses. These may be used to determine if a row and bank address received as part of an access operation are an aggressor row and bank address. The aggressor row address may be used to generate a refresh address for a bank identified by the aggressor bank address. Since the aggressor storage structure tracks both row and bank addresses, its storage space may be dynamically allocated between banks based on access patterns to those banks.