公开(公告)号：US10283187B2

公开(公告)日：2019-05-07

申请号：US15783688

申请日：2017-10-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis ,  Dragos Dimitriu

IPC: G11C7/22 ,  G11C11/4074 ,  G11C11/4076

Abstract: Apparatuses and methods for providing additional drive to multilevel signals representing data are described. An example apparatus includes a first driver section, a second driver section, and a third driver section. The first driver section is configured to drive an output terminal toward a first selected one of a first voltage and a second voltage. The second driver section configured to drive the output terminal toward a second selected one of the first voltage and the second voltage. The third driver section configured to drive the output terminal toward the first voltage when each of the first selected one and the second selected one is the first voltage. The third driver circuit is further configured to be in a high impedance state when the first selected one and the second selected one are different from each other.

公开(公告)号：US20190109755A1

公开(公告)日：2019-04-11

申请号：US16216742

申请日：2018-12-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis ,  Dean Gans ,  Randon Richards ,  Bruce W. Schober

IPC: H04L12/24 ,  H04L12/863 ,  H04L25/03

Abstract: According to one embodiment, A data buffer is described. The data buffer comprises a first input/output circuit configured to receive and provide a first signal encoded according to a first communications protocol, a second input/output circuit configured to receive and provide a second signal encoded according to a second communications protocol, and a conversion circuit coupled to the first and second input/output circuits and configured to convert the first signal to the second signal and to convert the second signal to the first signal.

公开(公告)号：US20190108864A1

公开(公告)日：2019-04-11

申请号：US16045468

申请日：2018-07-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis

IPC: G11C7/10 ,  G11C8/10

CPC classification number: G11C7/1006 ,  G11C8/10 ,  H03M1/361

Abstract: Apparatuses and methods for a multi-level communication architectures are disclosed herein. An example apparatus may include an input/output (I/O) circuit comprising a driver circuit configured to convert a first bitstream directed to a first memory device and a second bitstream directed to a second memory device into a single multilevel signal. The driver circuit is further configured to drive the multilevel signal onto a signal line coupled to the first memory device and to the second memory device using a driver configured to drive more than two voltages.

公开(公告)号：US20190044766A1

公开(公告)日：2019-02-07

申请号：US15885536

申请日：2018-01-31

Applicant: Micron Technology, Inc.

Inventor： Feng Lin ,  Timothy M. Hollis

IPC: H04L25/49 ,  G11C7/20 ,  H04L7/00 ,  H04L25/03

CPC classification number: H04L25/4917 ,  G11C7/1057 ,  G11C7/1063 ,  G11C7/1069 ,  G11C7/1084 ,  G11C7/1096 ,  G11C7/20 ,  H04L7/0037 ,  H04L25/03038 ,  H04L25/03343 ,  H04L2025/03363

Abstract: A memory interface may include a transmitter that generates multi-level signals made up of symbols that convey multiple bits of data. The transmitter may include a first data path for a first bit (e.g., a least significant bit (LSB)) in a symbol and a second data path for a second bit (e.g., the most significant bit (MSB)) in the symbol. Each path may include a de-emphasis or pre-emphasis buffer circuit that inverts and delays signals received at the de-emphasis or pre-emphasis buffer circuit. The delayed and inverted data signals may control de-emphasis or pre-emphasis drivers that are configured to apply de-emphasis or pre-emphasis to a multi-level signal.

公开(公告)号：US10146614B2

公开(公告)日：2018-12-04

申请号：US14833876

申请日：2015-08-24

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis

IPC: G11C29/00 ,  G11C7/00 ,  H03M13/00 ,  G06F11/10

Abstract: In one embodiment, a set of memory circuits is separated from a logic system by a bus. The logic system can contain many of the logic functions traditionally performed on conventional memory circuits, and accordingly the memory circuits can be modified to not include such logic functions. The logic system, which can be a logic integrated circuit intervening between the modified-memory circuits and a traditional memory controller, additionally contains encoding and decoding circuitry. In such a system, data are encoded and at least one indicator bit is issued when writing to the modified-memory circuits. The modified-memory circuits in turn store the at least one indicator bit with the encoded data. When the encoded data are read from the modified-memory circuits, the data are transmitted across the bus in their encoded state along with the at least one indicator bit. The logic integrated circuit then decodes the data using the at least one indicator bit to return the data to their original states. Other systems and methods are disclosed.

公开(公告)号：US09405874B2

公开(公告)日：2016-08-02

申请号：US14724554

申请日：2015-05-28

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: Methods and apparatuses disclose various embodiments of time-domain signal generation. In one embodiment a method includes receiving an input waveform having a plurality of cycles with aspects of the input waveform being input and controllable by an end-user. A set of transform coefficients is calculated for at least some of the cycles using at least one hardware-based processor. A time-domain cycle is calculated for each set of transform coefficients. Other methods and apparatuses are disclosed.

Abstract translation: 方法和装置公开了时域信号产生的各种实施例。 在一个实施例中，一种方法包括接收具有多个周期的输入波形，其中输入波形的方面由最终用户输入和控制。 使用至少一个基于硬件的处理器针对至少一些周期来计算一组变换系数。 为每组变换系数计算时域周期。 公开了其他方法和装置。

公开(公告)号：US20140301499A1

公开(公告)日：2014-10-09

申请号：US14308122

申请日：2014-06-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis

IPC: H04L25/49 ,  H04L25/02 ,  H04L1/22

CPC classification number: H04L25/4917 ,  G11C5/02 ,  H01L22/22 ,  H01L23/481 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2924/0002 ,  H04L1/22 ,  H04L25/0264 ,  H01L2924/00

Abstract: Apparatus are disclosed, such as those involving a 3-D integrated circuit. One such apparatus includes a first die including a plurality of vertical connectors formed therethrough. The apparatus also includes a first circuit configured to encode multiple data bits into a multi-bit symbol, and provide the multi-bit symbol to two or more of the vertical connectors. The apparatus further includes a second circuit configured to receive the multi-bit symbol from at least one of the two or more vertical connectors, and decode the multi-bit symbol into the multiple data bits. The apparatus provides enhanced repairability with no or less redundant vertical connectors, thus avoiding the need for “on the fly” or field repair of defective vertical connectors.

Abstract translation: 公开了诸如涉及3-D集成电路的装置。 一种这样的设备包括：第一模具，其包括穿过其形成的多个垂直连接件。 该装置还包括配置成将多个数据位编码为多位符号的第一电路，并将多位符号提供给两个或多个垂直连接器。 所述设备还包括被配置为从所述两个或更多个垂直连接器中的至少一个接收多位符号并将多位符号解码为多个数据位的第二电路。 该设备提供增强的可修复性，没有或多少冗余的垂直连接器，从而避免了对“有故障的”垂直连接器进行“即时”或现场维修的需要。

公开(公告)号：US20140125424A1

公开(公告)日：2014-05-08

申请号：US14153580

申请日：2014-01-13

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis ,  Steven Bodily

IPC: H04B3/28

CPC classification number: H03H7/0138 ,  H01L23/642 ,  H01L28/20 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor dies and methods are described, such as those including a first capacitive pathway having a first effective series resistance (ESR) and a second capacitive pathway having an adjustable ESR. One such device provides for optimizing the semiconductor die for different operating conditions such as operating frequency. As a result, semiconductor dies can be manufactured in a single configuration for several different operating frequencies, and each die can be tuned to reduce (e.g. minimize) supply noise, such as by varying the ESR or the capacitance of at least one of the pathways.

Abstract translation: 描述了半导体管芯和方法，例如包括具有第一有效串联电阻（ESR）的第一电容通路和具有可调节ESR的第二电容通路的那些。 一种这样的器件提供用于在诸如工作频率的不同操作条件下优化半导体管芯。 结果，可以以单个配置制造半导体管芯用于几个不同的工作频率，并且可以调整每个管芯以减小（例如最小化）电源噪声，例如通过改变至少一个通路的ESR或电容 。

公开(公告)号：US20140074446A1

公开(公告)日：2014-03-13

申请号：US14083062

申请日：2013-11-18

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: Methods and apparatus disclosed herein operate to receive a plurality of cycles characterized by a set of time-domain aspects, to modify at least one of the time-domain aspects of at least some of the plurality of cycles to produce a plurality of modified cycles, to process at least some of the modified cycles to produce time-domain cycles, and to create a time-domain signal based at least in part on concatenating the time-domain cycles.

Abstract translation: 本文公开的方法和装置操作以接收由一组时域方面表征的多个周期，以修改多个周期中的至少一些周期的时域方面中的至少一个以产生多个修改周期， 以处理至少一些经修改的周期以产生时域周期，并且至少部分地基于连接时域周期来创建时域信号。

公开(公告)号：US20250157909A1

公开(公告)日：2025-05-15

申请号：US19022030

申请日：2025-01-15

Applicant: Micron Technology, Inc.

Inventor： David K. Ovard ,  Thomas Hein ,  Timothy M. Hollis ,  Walter L. Moden

IPC: H01L23/498 ,  H01L23/00

Abstract: Apparatuses may include a device substrate including a microelectronic device and bond pads proximate to an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball of the ball grid array positioned and configured to carry one of a high-bandwidth data signal or a high-frequency clock signal is located laterally or longitudinally adjacent to no more than two other balls of the ball grid array configured to carry another of a high-bandwidth data signal or a high-frequency clock signal.