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公开(公告)号：US20090122602A1
公开(公告)日：2009-05-14
申请号：US12352668
申请日：2009-01-13
CPC分类号： G11C13/0069 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/004 , G11C2213/79
摘要： There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.
摘要翻译： 实现了高集成度和高速度的非易失性存储器，其可以在短的操作周期时间内稳定相变存储器的操作。 在写入驱动器中提供锁存器。 通过写使能信号，每列循环执行相变元件的高电阻状态的改变，并且在预充电命令被输入之后执行到其低电阻状态的改变，并且同时具有去激活 的预充电信号。 由此，对相变电阻变为低电阻状态的存储单元的写入时间，以及从相变电阻改变为高电阻状态到读操作的写操作的周期 可以延长上述存储单元，而不延长列周期时间，从而实现稳定的写操作。
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公开(公告)号：US07443721B2
公开(公告)日：2008-10-28
申请号：US11341385
申请日：2006-01-30
申请人： Kenzo Kurotsuchi , Kiyoo Itoh , Norikatsu Takaura , Kenichi Osada
发明人： Kenzo Kurotsuchi , Kiyoo Itoh , Norikatsu Takaura , Kenichi Osada
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C2013/0047 , G11C2013/0073 , G11C2013/0078 , G11C2013/0092 , G11C2213/79
摘要： A semiconductor non volatile memory device capable of multiple write operations with high reliability includes memory cells. Each memory cell of the device has a first electrode, a second electrode, and an information storage section between the two electrodes. A segregation of composing elements of the information storage section caused by applying a first current pulse from the first electrode to the second electrode is corrected by applying a second current pulse from the second electrode to the first electrode such that the composition of the storage section recovers to its original state.
摘要翻译： 能够具有高可靠性的多次写入操作的半导体非易失性存储器件包括存储单元。 器件的每个存储单元具有第一电极，第二电极和两个电极之间的信息存储部分。 通过从第二电极向第一电极施加第二电流脉冲来校正由第一电极向第二电极施加第一电流脉冲而引起的信息存储部分的组成元件的分离，使得存储部分的组成恢复 到原来的状态。
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公开(公告)号：US07154788B2
公开(公告)日：2006-12-26
申请号：US10995198
申请日：2004-11-24
IPC分类号： G11C11/34
CPC分类号： G11C13/0069 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/004 , G11C2213/79
摘要： There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.
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64.发明授权Hybrid semiconductor device having an n+ (p) doped n-type gate and method of producing the same 有权具有n +（p）掺杂n型栅极的混合半导体器件及其制造方法公开(公告)号：US07057243B2
公开(公告)日：2006-06-06
申请号：US10648883
申请日：2003-08-27
申请人： Satoru Yamada , Ryo Nagai , Kiyonori Oyu , Ryoichi Nakamura , Norikatsu Takaura
发明人： Satoru Yamada , Ryo Nagai , Kiyonori Oyu , Ryoichi Nakamura , Norikatsu Takaura
IPC分类号： H01L29/94
CPC分类号： H01L27/10891 , H01L21/28061 , H01L21/823842 , H01L27/10894 , H01L27/10897 , H01L29/4941 , H01L29/7833
摘要： In a semiconductor device of a polysilicon gate electrode structure having three or more different Fermi levels, a P type polysilicon having a lowest Fermi level is disposed on a first N type surface channel MOS transistor. A first N type polysilicon having a highest Fermi level is disposed on a second N type surface channel MOS transistor. A second N type polysilicon having an intermediate Fermi level between the highest and the lowest Fermi levels and doped with both an N type impurity and a P type impurity is disposed on a P channel MOS transistor.
摘要翻译： 在具有三个或更多个不同费米能级的多晶硅栅电极结构的半导体器件中，具有最低费米能级的P型多晶硅设置在第一N型表面沟道MOS晶体管上。 具有最高费米能级的第一N型多晶硅被布置在第二N型表面沟道MOS晶体管上。 具有最高和最低费米能级之间的中间费米能级并且掺杂有N型杂质和P型杂质的第二N型多晶硅设置在P沟道MOS晶体管上。
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公开(公告)号：US08866120B2
公开(公告)日：2014-10-21
申请号：US13314165
申请日：2011-12-07
申请人： Yuichi Matsui , Nozomu Matsuzaki , Norikatsu Takaura , Naoki Yamamoto , Hideyuki Matsuoka , Tomio Iwasaki
发明人： Yuichi Matsui , Nozomu Matsuzaki , Norikatsu Takaura , Naoki Yamamoto , Hideyuki Matsuoka , Tomio Iwasaki
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.
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公开(公告)号：US07613038B2
公开(公告)日：2009-11-03
申请号：US12352668
申请日：2009-01-13
IPC分类号： G11C7/00
CPC分类号： G11C13/0069 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/004 , G11C2213/79
摘要： There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.
摘要翻译： 实现了高集成度和高速度的非易失性存储器，其可以在短的操作周期时间内稳定相变存储器的操作。 在写入驱动器中提供锁存器。 通过写使能信号，每列循环执行相变元件的高电阻状态的改变，并且在预充电命令被输入之后执行到其低电阻状态的改变，并且同时具有去激活 的预充电信号。 由此，对相变电阻变为低电阻状态的存储单元的写入时间，以及从相变电阻改变为高电阻状态到读操作的写操作的周期 可以延长上述存储单元，而不延长列周期时间，从而实现稳定的写操作。
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公开(公告)号：US20090231913A1
公开(公告)日：2009-09-17
申请号：US12090375
申请日：2005-10-17
CPC分类号： G11C13/0069 , G11C7/04 , G11C13/0004 , G11C2013/009 , G11C2013/0092 , G11C2213/79
摘要： There is provided a technique capable of improving speed of a set operation, which controls writing rate in a semiconductor device including a memory cell using a phase-change material. The technique uses means for setting a set-pulse voltage to be applied to the phase-change material to have two steps: the first-step voltage sets a temperature of the phase-change memory to a temperature at which the fastest nucleation is obtained; and the second pulse sets the temperature to a temperature at which the fastest crystal growth is obtained, thereby obtaining solid-phase growth of the phase-change material without melting. Moreover, the technique uses means for controlling the two-step voltage applied to the phase-change memory by a two-step voltage applied to a word line capable of reducing the drain current variation.
摘要翻译： 提供了一种能够提高设定操作的速度的技术，其控制包括使用相变材料的存储单元的半导体器件的写入速度。 该技术使用用于设定要施加到相变材料的设定脉冲电压的装置以具有两个步骤：第一步骤电压将相变存储器的温度设置为获得最快成核的温度; 并且第二脉冲将温度设定为获得最快的晶体生长的温度，从而获得相变材料的固相生长而不熔化。 此外，该技术使用用于通过施加到能够减小漏极电流变化的字线的两级电压来控制施加到相变存储器的两级电压的装置。
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公开(公告)号：US07492644B2
公开(公告)日：2009-02-17
申请号：US11832727
申请日：2007-08-02
IPC分类号： G11C7/00
CPC分类号： G11C13/0069 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/004 , G11C2213/79
摘要： There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.
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公开(公告)号：US20070029676A1
公开(公告)日：2007-02-08
申请号：US11489668
申请日：2006-07-20
IPC分类号： H01L23/52
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： A resistor element formed of a peel-preventive film, a recording layer made of chalcogenide, and an upper electrode film is formed on a semiconductor substrate, first and second insulation films are formed so as to cover the resistor element, a via hole for exposing the upper electrode film is formed through the first and second insulation films, and a plug for electrical connection to the upper electrode film is formed in the via hole. To form the via hole, the first insulation film made of silicon nitride is used as an etching stopper to perform dry etching on the second insulation film. Then, dry etching is performed on the first insulation film to expose the upper electrode film from the via hole.
摘要翻译： 在半导体衬底上形成由防腐蚀膜，由硫族化物制成的记录层和上电极膜形成的电阻元件，形成第一和第二绝缘膜以覆盖电阻元件，用于暴露的通孔 上电极膜通过第一和第二绝缘膜形成，并且在通孔中形成用于与上电极膜电连接的插头。 为了形成通孔，将由氮化硅制成的第一绝缘膜用作蚀刻停止件，以在第二绝缘膜上进行干蚀刻。 然后，对第一绝缘膜进行干法蚀刻，以使上电极膜从通孔露出。
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公开(公告)号：US06943373B2
公开(公告)日：2005-09-13
申请号：US10693987
申请日：2003-10-28
申请人： Norikatsu Takaura , Hideyuki Matsuoka , Riichiro Takemura , Kousuke Okuyama , Masahiro Moniwa , Akio Nishida , Kota Funayama , Tomonori Sekiguchi
发明人： Norikatsu Takaura , Hideyuki Matsuoka , Riichiro Takemura , Kousuke Okuyama , Masahiro Moniwa , Akio Nishida , Kota Funayama , Tomonori Sekiguchi
IPC分类号： G11C11/41 , H01L21/8234 , H01L21/8244 , H01L27/00 , H01L27/06 , H01L27/088 , H01L27/10 , H01L27/11 , H01L29/10 , H01L29/72
CPC分类号： H01L27/11 , H01L27/0688 , H01L27/1104
摘要： The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.
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