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公开(公告)号：US20070070716A1
公开(公告)日：2007-03-29
申请号：US11598702
申请日：2006-11-14
IPC分类号： G11C7/10
CPC分类号： G11C13/0069 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/004 , G11C2213/79
摘要： There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.
摘要翻译： 实现了高集成度和高速度的非易失性存储器，其可以在短的操作周期时间内稳定相变存储器的操作。 在写入驱动器中提供锁存器。 通过写使能信号，每列循环执行相变元件的高电阻状态的改变，并且在预充电命令被输入之后执行到其低电阻状态的改变，并且同时具有去激活 的预充电信号。 由此，对相变电阻变为低电阻状态的存储单元的写入时间，以及从相变电阻改变为高电阻状态到读操作的写操作的周期 可以延长上述存储单元，而不延长列周期时间，从而实现稳定的写操作。
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公开(公告)号：US20050237820A1
公开(公告)日：2005-10-27
申请号：US10995198
申请日：2004-11-24
CPC分类号： G11C13/0069 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/004 , G11C2213/79
摘要： There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.
摘要翻译： 实现了高集成度和高速度的非易失性存储器，其可以在短的操作周期时间内稳定相变存储器的操作。 在写入驱动器中提供锁存器。 通过写使能信号，每列循环执行相变元件的高电阻状态的改变，并且在预充电命令被输入之后执行到其低电阻状态的改变，并且同时具有去激活 的预充电信号。 由此，对相变电阻变为低电阻状态的存储单元的写入时间，以及从相变电阻改变为高电阻状态到读操作的写操作的周期 可以延长上述存储单元，而不延长列周期时间，从而实现稳定的写操作。
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公开(公告)号：US20090122602A1
公开(公告)日：2009-05-14
申请号：US12352668
申请日：2009-01-13
CPC分类号： G11C13/0069 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/004 , G11C2213/79
摘要： There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.
摘要翻译： 实现了高集成度和高速度的非易失性存储器，其可以在短的操作周期时间内稳定相变存储器的操作。 在写入驱动器中提供锁存器。 通过写使能信号，每列循环执行相变元件的高电阻状态的改变，并且在预充电命令被输入之后执行到其低电阻状态的改变，并且同时具有去激活 的预充电信号。 由此，对相变电阻变为低电阻状态的存储单元的写入时间，以及从相变电阻改变为高电阻状态到读操作的写操作的周期 可以延长上述存储单元，而不延长列周期时间，从而实现稳定的写操作。
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公开(公告)号：US07154788B2
公开(公告)日：2006-12-26
申请号：US10995198
申请日：2004-11-24
IPC分类号： G11C11/34
CPC分类号： G11C13/0069 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/004 , G11C2213/79
摘要： There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.
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公开(公告)号：US07613038B2
公开(公告)日：2009-11-03
申请号：US12352668
申请日：2009-01-13
IPC分类号： G11C7/00
CPC分类号： G11C13/0069 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/004 , G11C2213/79
摘要： There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.
摘要翻译： 实现了高集成度和高速度的非易失性存储器，其可以在短的操作周期时间内稳定相变存储器的操作。 在写入驱动器中提供锁存器。 通过写使能信号，每列循环执行相变元件的高电阻状态的改变，并且在预充电命令被输入之后执行到其低电阻状态的改变，并且同时具有去激活 的预充电信号。 由此，对相变电阻变为低电阻状态的存储单元的写入时间，以及从相变电阻改变为高电阻状态到读操作的写操作的周期 可以延长上述存储单元，而不延长列周期时间，从而实现稳定的写操作。
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公开(公告)号：US07492644B2
公开(公告)日：2009-02-17
申请号：US11832727
申请日：2007-08-02
IPC分类号： G11C7/00
CPC分类号： G11C13/0069 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/004 , G11C2213/79
摘要： There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.
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公开(公告)号：US07257034B2
公开(公告)日：2007-08-14
申请号：US11598702
申请日：2006-11-14
IPC分类号： G11C11/34
CPC分类号： G11C13/0069 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/004 , G11C2213/79
摘要： There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.
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公开(公告)号：US07619911B2
公开(公告)日：2009-11-17
申请号：US10579911
申请日：2003-11-21
申请人： Satoru Hanzawa , Junji Shigeta , Shinichiro Kimura , Takeshi Sakata , Riichiro Takemura , Kazuhiko Kajigaya
发明人： Satoru Hanzawa , Junji Shigeta , Shinichiro Kimura , Takeshi Sakata , Riichiro Takemura , Kazuhiko Kajigaya
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C15/043
摘要： In a memory array structured of memory cells using a storage circuit STC and a comparator CP, either one electrode of a source electrode or a drain electrode of a transistor, whose gate electrode is connected to a search line, of a plurality of transistors structuring the comparator CP is connected to a match line HMLr precharged to a high voltage. Further, a match detector MDr is arranged on a match line LMLr precharged to a low voltage to discriminate a comparison signal voltage generated at the match line according to the comparison result of data. According to such memory array structure and operation, comparison operation can be performed at low power and at high speed while influence of search-line noise is avoided in a match line pair. Therefore, a low power content addressable memory which allows search operation at high speed can be realized.
摘要翻译： 在使用存储电路STC和比较器CP的存储器单元构成的存储器阵列中，将栅电极连接到搜索线的晶体管的源电极或漏电极的一个电极，构成 比较器CP连接到预充电到高电压的匹配线HMLr。 此外，匹配检测器MDr布置在预充电到低电压的匹配线LMLr上，以根据数据的比较结果来识别在匹配线处产生的比较信号电压。 根据这种存储器阵列结构和操作，可以在低功率和高速度下执行比较操作，同时在匹配线对中避免搜索线噪声的影响。 因此，可以实现允许高速搜索操作的低功率内容可寻址存储器。
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公开(公告)号：US20050056876A1
公开(公告)日：2005-03-17
申请号：US10975494
申请日：2004-10-29
申请人： Shinichi Miyatake , Kazuhiko Kajigaya , Kazuyuki Miyazawa , Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata
发明人： Shinichi Miyatake , Kazuhiko Kajigaya , Kazuyuki Miyazawa , Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata
IPC分类号： G11C11/401 , G11C7/18 , G11C11/403 , G11C11/405 , G11C11/406 , G11C11/4097 , H01L21/8242 , H01L27/02 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/0328 , H01L31/119
CPC分类号： H01L27/108 , G11C7/18 , G11C11/403 , G11C11/406 , G11C11/40615 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/10814 , H01L27/10885 , H01L27/10897 , Y10S257/905 , Y10S257/906
摘要： A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell·two cells/bit method has a twin cell structure employing a one-intersection 6 F2 cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2 F and smaller than 4 F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.
摘要翻译： 提供一种半导体存储器件，其可以通过减少存储器单元的面积的增加并获得超宽带的周期，实现信息保持时间期间的高集成度，超高速度运行和功耗的显着降低， 高速读出时间，确保自刷新时间长的刷新周期。 采用单交点单元两个单元/位方法的DRAM具有采用单交叉6 F 2单元的双单元结构，其结构是：存储单元布置在对应于a 位线对和字线; 并且当字线的半间距被定义为F时，位线对的每个位线的间距大于2F且小于4F。另外，硅衬底中的有源区域 形成每个存储单元的晶体管的源极，沟道和漏极，相对于位线对的方向倾斜地形成。
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公开(公告)号：US06992343B2
公开(公告)日：2006-01-31
申请号：US10975494
申请日：2004-10-29
申请人： Shinichi Miyatake , Kazuhiko Kajigaya , Kazuyuki Miyazawa , Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata
发明人： Shinichi Miyatake , Kazuhiko Kajigaya , Kazuyuki Miyazawa , Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/108 , G11C7/18 , G11C11/403 , G11C11/406 , G11C11/40615 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/10814 , H01L27/10885 , H01L27/10897 , Y10S257/905 , Y10S257/906
摘要： A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell·two cells/bit method has a twin cell structure employing a one-intersection 6F2 cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2F and smaller than 4F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.
摘要翻译： 提供一种半导体存储器件，其可以通过减少存储器单元的面积的增加并获得超宽带的周期来实现信息保持时间期间的高集成度，超高速度运行和功耗的显着降低， 高速读出时间，确保自刷新时间长的刷新周期。 采用单交点单元两个单元/比特方法的DRAM具有采用单交叉6F 单元的双单元结构，其结构是：将存储单元布置在与 位线对和字线之间的交点; 并且当字线的半间距被定义为F时，位线对的每个位线的间距大于2F且小于4F。 此外，在硅衬底中形成每个存储单元的晶体管的源极，沟道和漏极的有源区相对于位线对的方向倾斜地形成。
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