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    Semiconductor integrated circuit device
    1.
    发明申请
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US20070070716A1

    公开(公告)日：2007-03-29

    申请号：US11598702

    申请日：2006-11-14

    申请人： Riichiro Takemura ,  Takeshi Sakata ,  Norikatsu Takaura ,  Kazuhiko Kajigaya

    发明人： Riichiro Takemura ,  Takeshi Sakata ,  Norikatsu Takaura ,  Kazuhiko Kajigaya

    IPC分类号： G11C7/10

    CPC分类号： G11C13/0069 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1096 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/004 ,  G11C2213/79

    摘要： There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.

    摘要翻译： 实现了高集成度和高​​速度的非易失性存储器，其可以在短的操作周期时间内稳定相变存储器的操作。 在写入驱动器中提供锁存器。 通过写使能信号，每列循环执行相变元件的高电阻状态的改变，并且在预充电命令被输入之后执行到其低电阻状态的改变，并且同时具有去激活 的预充电信号。 由此，对相变电阻变为低电阻状态的存储单元的写入时间，以及从相变电阻改变为高电阻状态到读操作的写操作的周期 可以延长上述存储单元，而不延长列周期时间，从而实现稳定的写操作。

    Semiconductor integrated circuit device
    2.
    发明申请
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US20050237820A1

    公开(公告)日：2005-10-27

    申请号：US10995198

    申请日：2004-11-24

    申请人： Riichiro Takemura ,  Takeshi Sakata ,  Norikatsu Takaura ,  Kazuhiko Kajigaya

    发明人： Riichiro Takemura ,  Takeshi Sakata ,  Norikatsu Takaura ,  Kazuhiko Kajigaya

    IPC分类号： G11C11/42 ,  G11C5/00 ,  G11C7/00 ,  G11C8/08 ,  G11C11/419 ,  G11C13/02

    CPC分类号： G11C13/0069 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1096 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/004 ,  G11C2213/79

    摘要： There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.

    摘要翻译： 实现了高集成度和高​​速度的非易失性存储器，其可以在短的操作周期时间内稳定相变存储器的操作。 在写入驱动器中提供锁存器。 通过写使能信号，每列循环执行相变元件的高电阻状态的改变，并且在预充电命令被输入之后执行到其低电阻状态的改变，并且同时具有去激活 的预充电信号。 由此，对相变电阻变为低电阻状态的存储单元的写入时间，以及从相变电阻改变为高电阻状态到读操作的写操作的周期 可以延长上述存储单元，而不延长列周期时间，从而实现稳定的写操作。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    3.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
    半导体集成电路设备

    公开(公告)号：US20090122602A1

    公开(公告)日：2009-05-14

    申请号：US12352668

    申请日：2009-01-13

    申请人： RIICHIRO TAKEMURA ,  Takeshi Sakata ,  Norikatsu Takaura ,  Kazuhiko Kajigaya

    发明人： RIICHIRO TAKEMURA ,  Takeshi Sakata ,  Norikatsu Takaura ,  Kazuhiko Kajigaya

    IPC分类号： G11C11/00 ,  G11C8/08 ,  G11C7/00

    CPC分类号： G11C13/0069 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1096 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/004 ,  G11C2213/79

    摘要： There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.

    摘要翻译： 实现了高集成度和高​​速度的非易失性存储器，其可以在短的操作周期时间内稳定相变存储器的操作。 在写入驱动器中提供锁存器。 通过写使能信号，每列循环执行相变元件的高电阻状态的改变，并且在预充电命令被输入之后执行到其低电阻状态的改变，并且同时具有去激活 的预充电信号。 由此，对相变电阻变为低电阻状态的存储单元的写入时间，以及从相变电阻改变为高电阻状态到读操作的写操作的周期 可以延长上述存储单元，而不延长列周期时间，从而实现稳定的写操作。

    Semiconductor integrated circuit device
    5.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US07613038B2

    公开(公告)日：2009-11-03

    申请号：US12352668

    申请日：2009-01-13

    申请人： Riichiro Takemura ,  Takeshi Sakata ,  Norikatsu Takaura ,  Kazuhiko Kajigaya

    发明人： Riichiro Takemura ,  Takeshi Sakata ,  Norikatsu Takaura ,  Kazuhiko Kajigaya

    IPC分类号： G11C7/00

    CPC分类号： G11C13/0069 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1096 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/004 ,  G11C2213/79

    摘要： There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.

    摘要翻译： 实现了高集成度和高​​速度的非易失性存储器，其可以在短的操作周期时间内稳定相变存储器的操作。 在写入驱动器中提供锁存器。 通过写使能信号，每列循环执行相变元件的高电阻状态的改变，并且在预充电命令被输入之后执行到其低电阻状态的改变，并且同时具有去激活 的预充电信号。 由此，对相变电阻变为低电阻状态的存储单元的写入时间，以及从相变电阻改变为高电阻状态到读操作的写操作的周期 可以延长上述存储单元，而不延长列周期时间，从而实现稳定的写操作。

    Semiconductor device with a non-erasable memory and/or a nonvolatile memory
    8.
    发明授权
    Semiconductor device with a non-erasable memory and/or a nonvolatile memory 失效
    具有不可擦除存储器和/或非易失性存储器的半导体器件

    公开(公告)号：US07385838B2

    公开(公告)日：2008-06-10

    申请号：US11715918

    申请日：2007-03-09

    申请人： Kenichi Osada ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki ,  Takayuki Kawahara

    发明人： Kenichi Osada ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki ,  Takayuki Kawahara

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0004 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/3454 ,  G11C2013/0092 ,  G11C2213/82

    摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.

    摘要翻译： 一种半导体器件包括多个存储单元，一个中央处理单元，一个复位时间的定时器电路，以及一个定时器电路，该定时器电路需要一个SET时间。 每个存储单元的NMOS晶体管的阈值电压低于外围电路的阈值电压，从而容易地执行复位操作。 流过电流的方向在复位操作和SET操作中改变，位线被高速激活，从而防止系统故障。 此外，半导体器件可以克服由于核心电压（例如1.2V）下操作具有最小尺寸CMOS晶体管的相位变化元件时CMOS晶体管的变化而导致的错误写入操作和数据破坏的问题。 根据本发明，可以使用最小尺寸的单元晶体管在低电压下实现稳定的操作。