公开(公告)号：US20140264925A1

公开(公告)日：2014-09-18

申请号：US13867905

申请日：2013-04-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L23/535 ,  H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/76807 ,  H01L21/76838 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

Abstract: A 3-D structure includes a stack of active layers at different depths has a plurality of contact landing areas on respective active layers within a contact area opening. A plurality of interlayer conductors, each includes a first portion within a contact area opening extending to a contact landing area, and a second portion in part outside the contact area opening above the top active layer. The first portion has a transverse dimension Y1 that is nominally equal to the transverse dimension of the contact area opening, and the second portion having a transverse dimension Y2 that is greater than the transverse dimension of the contact area opening. The active layers can be bit lines or word lines for a 3-D memory device, or other active layers in integrated circuits.

Abstract translation: 3-D结构包括不同深度的有源层堆叠在接触区域开口内的相应有源层上具有多个接触着陆区域。 多个层间导体各自包括在延伸到接触着陆区域的接触区域开口内的第一部分和位于顶部活性层上方的接触区域的部分外部的第二部分。 第一部分具有名义上等于接触区域开口的横向尺寸的横向尺寸Y1，并且第二部分具有大于接触区域开口的横向尺寸的横向尺寸Y2。 有源层可以是用于3-D存储器件或集成电路中的其它有源层的位线或字线。

公开(公告)号：USRE50357E1

公开(公告)日：2025-03-25

申请号：US17892183

申请日：2022-08-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L27/115 ,  H10B43/10 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27

Abstract: A 3D semiconductor device is provided, comprising plural memory layers vertically stacked on a substrate and parallel to each other; plural selection lines disposed on the memory layers and parallel to each other; plural bit lines disposed on the selection lines, and the bit lines arranged in parallel to each other and in perpendicular to the selection lines; plural strings formed vertically to the memory layers and the selection lines, and the strings electrically connected to the corresponding selection lines; a plurality of cells respectively defined by the strings, the selection lines and the bit lines correspondingly, and the cells arranged in a plurality of rows and columns, wherein a column direction is parallel to the bit lines while a row direction is parallel to the selection lines. The adjacent cells in the same column are electrically connected to the different bit lines.

公开(公告)号：US12009053B2

公开(公告)日：2024-06-11

申请号：US17841866

申请日：2022-06-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: G11C7/12 ,  G11C8/14

CPC classification number: G11C7/12 ,  G11C8/14

Abstract: A data search method for a memory device is provided. The data search method includes: based on a recorded compression mode, vectoring a search data to generate a search data vector, and based on the recorded compression mode, compressing the search data and a plurality of objects in a database; setting a search condition; searching the objects of the database by the search data vector to determine whether the search data is matched with the objects of the database; and recording and outputting at least one matched object of the database, the at least one matched object matched with the search data.

公开(公告)号：US11894356B2

公开(公告)日：2024-02-06

申请号：US17403925

申请日：2021-08-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/05647 ,  H01L2224/08145

Abstract: A chip includes a substrate and a plurality of functional units on the substrate, in which each of the functional units has its own set of pads. The functional units are physically connected and there is no scribe line passes through the chip. A semiconductor structure having the chip is also disclosed.

公开(公告)号：US10332936B2

公开(公告)日：2019-06-25

申请号：US15490946

申请日：2017-04-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L29/788 ,  H01L27/24 ,  H01L21/768 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11524 ,  H01L27/11519 ,  H01L29/792 ,  H01L29/66 ,  H01L23/28 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

Abstract: A 3D stacking semiconductor device and a manufacturing method thereof are provided. The method includes using a set of N etch masks for creating O different numbers of removed layers in the conductive layers and the insulating layers for forming landing areas on the conductive layers in the contact region, each mask including mask and etch regions, N being an integer equal to or larger than 2, O being an integer larger than 2, 2N-1

公开(公告)号：US10082960B1

公开(公告)日：2018-09-25

申请号：US15465751

申请日：2017-03-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: G06F3/06 ,  G06F11/16 ,  G06F11/20

Abstract: A memory device is disclosed. The memory device includes a memory array. The memory array includes a main memory block and an extra memory block. The memory array includes a main bit line and an extra bit line. A ratio of a quantity of the extra memory block to a quantity of the main memory block is a block quantity ratio A. A ratio of a quantity of the extra bit line to a quantity of the main bit line is a bit line quantity ratio B. The block quantity ratio A is larger than the bit line quantity ratio B.

公开(公告)号：US10056371B2

公开(公告)日：2018-08-21

申请号：US15213522

申请日：2016-07-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L27/06 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11573 ,  H01L27/12 ,  H01L27/11551 ,  H01L27/11578

CPC classification number: H01L27/0688 ,  H01L27/11531 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1203

Abstract: A memory structure is provided. The memory structure includes a substrate, an array portion disposed on the substrate, a periphery portion disposed on the array portion, and a plurality of contacts connecting the array portion to the periphery portion.

公开(公告)号：USRE46522E1

公开(公告)日：2017-08-22

申请号：US14602158

申请日：2015-01-21

Applicant: Macronix International Co., Ltd.

Inventor： Hang-Ting Lue ,  Shih-Hung Chen

IPC: G11C16/00 ,  H01L29/792 ,  G11C16/34 ,  H01L29/66 ,  H01L27/11582 ,  G11C16/04 ,  H01L27/11578

CPC classification number: H01L29/7926 ,  G11C16/0466 ,  G11C16/3418 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833

Abstract: A memory device, a manufacturing method and an operating method of the same are provided. The memory device includes a substrate, stacked structures, a channel element, a dielectric element, a source element, and a bit line. The stacked structures are disposed on the substrate. Each of the stacked structures includes a string selection line, a word line, a ground selection line and an insulating line. The string selection line, the word line and the ground selection line are separated from each other by the insulating line. The channel element is disposed between the stacked structures. The dielectric element is disposed between the channel element and the stacked structure. The source element is disposed between the upper surface of the substrate and the lower surface of the channel element. The bit line is disposed on the upper surface of the channel element.

公开(公告)号：US09666532B2

公开(公告)日：2017-05-30

申请号：US15164730

申请日：2016-05-25

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen

IPC: H01L23/528 ,  H01L27/115 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/02 ,  H01L27/1157 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: Roughly described, a memory device has a multilevel stack of conductive layers. Vertically oriented pillars each include series-connected memory cells at cross-points between the pillars and the conductive layers. SSLs run above the conductive layers, each intersection of a pillar and an SSL defining a respective select gate of the pillar. Bit lines run above the SSLs. The pillars are arranged on a regular grid which is rotated relative to the bit lines. The grid may have a square, rectangle or diamond-shaped unit cell, and may be rotated relative to the bit lines by an angle θ where tan(θ)=±X/Y, where X and Y are co-prime integers. The SSLs may be made wide enough so as to intersect two pillars on one side of the unit cell, or all pillars of the cell, or sufficiently wide as to intersect pillars in two or more non-adjacent cells.

公开(公告)号：US20170069567A1

公开(公告)日：2017-03-09

申请号：US14845304

申请日：2015-09-04

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen

IPC: H01L23/528 ,  G11C16/08 ,  H01L27/115 ,  H01L29/792 ,  H01L29/788

CPC classification number: H01L23/528 ,  G11C16/08 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

Abstract: A memory structure is provided. The memory structure comprises M array regions and N contact regions. M is an integer ≧2. N is an integer ≧M. Each array region is coupled to at least one contact region. Each contact region comprises a stair structure and a plurality of contacts. The stair structure comprises alternately stacked conductive layers and insulating layers. Each contact is connected to one conductive layer of the stair structure. Two array regions which are adjacent to each other are spatially separated by two contact regions, which are coupled to the two array regions, respectively.

Abstract translation: 提供了存储器结构。 存储器结构包括M个阵列区和N个接触区。 M为≥2的整数。 N是整数≧M。 每个阵列区域耦合到至少一个接触区域。 每个接触区域包括楼梯结构和多个接触。 楼梯结构包括交替堆叠的导电层和绝缘层。 每个触点连接到楼梯结构的一个导电层。 彼此相邻的两个阵列区域由两个接触区域空间分开，两个接触区域分别耦合到两个阵列区域。