公开(公告)号：US07531850B2

公开(公告)日：2009-05-12

申请号：US11420876

申请日：2006-05-30

申请人： Richard A. Blanchard

发明人： Richard A. Blanchard

IPC分类号： H01L29/74 ,  H01L31/111

CPC分类号： H01L29/151 ,  B82Y10/00 ,  H01L29/152 ,  H01L29/74

摘要： A semiconductor device may include at least one memory cell comprising a negative differential resistance (NDR) device and a control gate coupled thereto. The NDR device may include a superlattice including a plurality of stacked groups of layers, with each group of layers of the superlattice including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

摘要翻译： 半导体器件可以包括至少一个包括负差分电阻（NDR）器件和与其耦合的控制栅极的存储器单元。 NDR器件可以包括超晶格，其包括多个堆叠的层组，超晶格的每组层包括限定基极半导体部分的多个层叠的基底半导体单层和限定在晶格内的至少一个非半导体单层 的相邻基底半导体部分。

公开(公告)号：US07504305B2

公开(公告)日：2009-03-17

申请号：US11343329

申请日：2006-01-31

申请人： Richard A. Blanchard

发明人： Richard A. Blanchard

IPC分类号： H01L21/336

CPC分类号： H01L27/088 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811

摘要： A method of manufacturing a semiconductor device is disclosed and starts with a semiconductor substrate having a heavily doped N region at the bottom main surface and having a lightly doped N region at the top main surface. There are a plurality of trenches in the substrate, with each trench having a first extending portion extending from the top main surface towards the heavily doped region. Each trench has two sidewall surfaces in parallel alignment with each other. A blocking layer is formed on the sidewalls and the bottom of each trench. Then a P type dopant is obliquely implanted into the sidewall surfaces to form P type doped regions. The blocking layer is then removed. The bottom of the trenches is then etched to remove any implanted P type dopants. The implants are diffused and the trenches are filled.

摘要翻译： 公开了一种制造半导体器件的方法，并且从在底部主表面上具有重掺杂N区并在顶部主表面上具有轻掺杂N区的半导体衬底开始。 衬底中存在多个沟槽，每个沟槽具有从顶部主表面朝向重掺杂区域延伸的第一延伸部分。 每个沟槽具有彼此平行对准的两个侧壁表面。 在每个沟槽的侧壁和底部上形成阻挡层。 然后将P型掺杂剂倾斜地注入到侧壁表面中以形成P型掺杂区域。 然后去除阻挡层。 然后蚀刻沟槽的底部以去除任何植入的P型掺杂剂。 植入物被扩散并且沟槽被填充。

公开(公告)号：US20080265317A1

公开(公告)日：2008-10-30

申请号：US12171734

申请日：2008-07-11

申请人： Richard A. Blanchard

发明人： Richard A. Blanchard

IPC分类号： H01L29/78

CPC分类号： H01L27/088 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811

摘要： A method of manufacturing a semiconductor device is disclosed and starts with a semiconductor substrate having a heavily doped N region at the bottom main surface and having a lightly doped N region at the top main surface. There are a plurality of trenches in the substrate, with each trench having a first extending portion extending from the top main surface towards the heavily doped region. Each trench has two sidewall surfaces in parallel alignment with each other. A blocking layer is formed on the sidewalls and the bottom of each trench. Then a P type dopant is obliquely implanted into the sidewall surfaces to form P type doped regions. The blocking layer is then removed. The bottom of the trenches is then etched to remove any implanted P type dopants. The implants are diffused and the trenches are filled.

摘要翻译： 公开了一种制造半导体器件的方法，并且从在底部主表面上具有重掺杂N区并在顶部主表面上具有轻掺杂N区的半导体衬底开始。 衬底中存在多个沟槽，每个沟槽具有从顶部主表面朝向重掺杂区域延伸的第一延伸部分。 每个沟槽具有彼此平行对准的两个侧壁表面。 在每个沟槽的侧壁和底部上形成阻挡层。 然后将P型掺杂剂倾斜地注入到侧壁表面中以形成P型掺杂区域。 然后去除阻挡层。 然后蚀刻沟槽的底部以去除任何植入的P型掺杂剂。 植入物被扩散并且沟槽被填充。

公开(公告)号：US07339252B2

公开(公告)日：2008-03-04

申请号：US11384565

申请日：2006-03-20

申请人： Richard A. Blanchard

发明人： Richard A. Blanchard

IPC分类号： H01L21/762

CPC分类号： H01L29/66712 ,  H01L21/26586 ,  H01L21/76208 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/66333

摘要： A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The method also includes providing in the semiconductor substrate one or more trenches, first mesas and second mesas. The method also includes oxidizing sidewalls and bottoms of each trench; depositing a doped oxide into each trench and on the tops of the first and second mesas; and thermally oxidizing the semiconductor substrate at a temperature sufficient enough to cause the deposited oxide to flow so that the silicon in each of the first mesas is completely converted to silicon dioxide while the silicon in each of the second mesas is only partially converted to silicon dioxide and so that each of the trenches is filled with oxide.

摘要翻译： 一种制造半导体器件的方法包括提供具有彼此相对的第一和第二主表面的半导体衬底。 该方法还包括在半导体衬底中提供一个或多个沟槽，第一台面和第二台面。 该方法还包括氧化每个沟槽的侧壁和底部; 将掺杂的氧化物沉积到第一和第二台面的每个沟槽和顶部; 以及在足以使沉积的氧化物流动的温度下热氧化半导体衬底，使得每个第一台面中的硅完全转化为二氧化硅，而每个第二台面中的硅仅部分转化为二氧化硅 并且使得每个沟槽都填充有氧化物。

公开(公告)号：US07244970B2

公开(公告)日：2007-07-17

申请号：US11020507

申请日：2004-12-22

申请人： Adrian I. Cogan ,  Jin Qiu ,  Richard A. Blanchard

发明人： Adrian I. Cogan ,  Jin Qiu ,  Richard A. Blanchard

IPC分类号： H01L29/72

CPC分类号： H01L29/66136 ,  H01L27/0255 ,  H01L29/861

摘要： A two-terminal barrier controlled TVS diode has a depletion region barrier blocking majority carrier flow through the channel region at the vicinity of the cathode region at bias levels below the predetermined clamping voltage applied between the anode electrode and the cathode electrode, and may be arranged such that the anode region provides conductivity modulation by injecting minority carriers into the channel region during conduction of the semiconductor structure. In presently preferred form the majority carriers are electrons and the minority carriers are holes. Fabrication methods are described.

摘要翻译： 两端势垒控制TVS二极管具有消耗区域阻挡阻挡多数载流子流过阴极区附近的沟道区域，该偏压电平低于施加在阳极电极和阴极电极之间的预定钳位电压的偏置电平，并且可布置 使得阳极区域在半导体结构的导通期间通过将少数载流子注入沟道区域来提供导电性调制。 在目前优选的形式中，多数载流子是电子，而少数载流子是空穴。 描述制造方法。

公开(公告)号：US07199427B2

公开(公告)日：2007-04-03

申请号：US11104088

申请日：2005-04-12

申请人： Richard A. Blanchard

发明人： Richard A. Blanchard

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7811 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7883

摘要： A DMOS device is provided which is equipped with a floating gate having a first and second electrode in close proximity thereto. The floating gate is separated from one of the first and second electrodes by a thin layer of dielectric material whose dimensions and composition permit charge carriers to tunnel through the dielectric layer either to or from the floating gate. This tunneling phenomenon can be used to create a threshold voltage that may be adjusted to provide a precise current by placing a voltage between a programming electrode and the body/source and gate electrode of the device.

摘要翻译： 提供了一种DMOS装置，其配备有具有紧邻其的第一和第二电极的浮动栅极。 浮动栅极通过介电材料的薄层与第一和第二电极中的一个分离，其尺寸和组成允许电荷载流子穿过介电层或者从浮动栅极穿过介电层。 这种隧道现象可以用于产生阈值电压，该阈值电压可以通过在编程电极与器件的主体/源极和栅极之间放置电压来提供精确的电流。

公开(公告)号：US07138289B2

公开(公告)日：2006-11-21

申请号：US10886435

申请日：2004-07-07

申请人： Richard A. Blanchard ,  Richard K. Robinson

发明人： Richard A. Blanchard ,  Richard K. Robinson

IPC分类号： H01L21/00

CPC分类号： H01L27/14645 ,  H01L27/14647 ,  H01L27/14683 ,  H01L27/14689

摘要： A multilayer color-sensing photodetector is fabricated in a semiconductor wafer having a single crystal structure to form a first, second and third layer of single crystal semiconductor material. A dielectric layer is formed that completely surrounds each single crystal region. A blocking layer is applied to prevent ion implantation where not desired. Ions are implanted into a predefined implant area. The semiconductor wafer is heated to create a dielectric layer part way through the single crystal semiconductor region. The second layer of single crystal semiconductor materials is formed by depositing a single crystal or polycrystalline material and annealing it to form a single crystal semiconductor. The deposited semiconductor layer is masked and etched to obtain single crystal regions directly above the previous layer. A blocking layer is applied and an ion implant is performed. After heating, there is left a region of single crystal silicon that has its sides and bottom surrounding by a dielectric border. The third layer of semiconductor material is likewise deposited and processed to form a top layer of single crystal semiconductor material.

摘要翻译： 在具有单晶结构的半导体晶片中制造多层色彩感测光电检测器，以形成第一，第二和第三层单晶半导体材料。 形成完全围绕每个单晶区域的电介质层。 施加阻挡层以防止不期望的离子注入。 离子植入预定义的植入区域。 半导体晶片被加热以产生穿过单晶半导体区域的介电层。 第二层单晶半导体材料通过沉积单晶或多晶材料并退火以形成单晶半导体而形成。 对沉积的半导体层进行掩模蚀刻以获得直接在上一层之上的单晶区域。 施加阻挡层并执行离子注入。 在加热之后，留下单面硅的区域，其侧面和底部围绕介质边界。 同样地，第三层半导体材料被沉积和加工以形成单晶半导体材料的顶层。

公开(公告)号：US06949432B2

公开(公告)日：2005-09-27

申请号：US10978932

申请日：2004-11-01

申请人： Richard A. Blanchard

发明人： Richard A. Blanchard

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L29/7809 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/7813

摘要： A trench DMOS transistor structure having a low resistance path to a drain contact located on an upper surface and methods of making the same. The transistor structure comprises: (1) a first region of semiconductor material of a first conductivity type; (2) a gate trench formed within the first region; (3) a layer of gate dielectric within the gate trench; (4) a gate electrode within the gate trench adjacent the layer of gate dielectric material; (5) a drain access trench formed within the first region; (6) a drain access region of conductive material located within the drain access trench; (7) a source region of the first conductivity type within the first region, the source region being at or near a top surface of the first region and adjacent to the gate trench; (8) a body region within the first region below the source region and adjacent to the gate trench, the body region having a second conductivity type opposite the first conductivity type; and (9) a second region of semiconductor material within the first region below the body region. The second region is of the first conductivity type and has a higher dopant concentration than the first semiconductor region. Moreover, the second region extends from the gate trench to the drain access trench and is self-aligned to both the gate trench and the drain access trench.

摘要翻译： 沟槽DMOS晶体管结构，其具有位于上表面上的漏极触点的低电阻路径及其制造方法。 晶体管结构包括：（1）第一导电类型的半导体材料的第一区域; （2）形成在第一区域内的栅极沟槽; （3）栅极沟槽内的栅极电介质层; （4）栅极沟槽内的与栅介质材料层相邻的栅电极; （5）形成在第一区域内的漏极接触沟槽; （6）位于所述漏极接入沟槽内的导电材料的漏极接近区域; （7）在第一区域内的第一导电类型的源极区域，源极区域在第一区域的顶表面处或附近，并且与栅极沟槽相邻; （8）在所述源极区域的下方并与所述栅极沟槽相邻的所述第一区域内的主体区域，所述主体区域具有与所述第一导电类型相反的第二导电类型; 和（9）位于所述身体区域下方的所述第一区域内的第二半导体材料区域。 第二区域是第一导电类型，并且具有比第一半导体区域更高的掺杂剂浓度。 此外，第二区域从栅极沟槽延伸到漏极接触沟槽，并且与栅极沟槽和漏极接触沟槽自对准。

公开(公告)号：US06812056B2

公开(公告)日：2004-11-02

申请号：US10382256

申请日：2003-03-05

申请人： Richard A. Blanchard

发明人： Richard A. Blanchard

IPC分类号： H01L2100

CPC分类号： B81B3/0035

摘要： A single crystal semiconductor region is fabricated in a semiconductor wafer. The region is either cantilevered, supported at one or both ends, or midpoint, or supported at multiple locations. After a pattern and etch step, a dielectric fill step is performed to define the boundaries of the region in the semiconductor wafer. Oxygen or nitrogen is implanted in the semiconductor wafer on a surface area of the semiconductor wafer that corresponds to a top surface of the region. The annealing of the oxygen or nitrogen ions convert the silicon to an oxide or a nitride beneath the surface area. The silicon dioxide or silicon nitride is etched away to produce a semiconducting region of a single crystal material.

摘要翻译： 在半导体晶片中制造单晶半导体区域。 该区域是悬臂式的，在一端或两端支撑或中点支撑，或在多个位置支撑。 在图案和蚀刻步骤之后，执行介电填充步骤以限定半导体晶片中的区域的边界。 在对应于该区域的上表面的半导体晶片的表面区域上，在半导体晶片中注入氧或氮。 氧或氮离子的退火将硅转化成表面积下面的氧化物或氮化物。 蚀刻掉二氧化硅或氮化硅以产生单晶材料的半导体区域。

公开(公告)号：US06713351B2

公开(公告)日：2004-03-30

申请号：US09819356

申请日：2001-03-28

申请人： Richard A. Blanchard

发明人： Richard A. Blanchard

IPC分类号： H01L21336

CPC分类号： H01L29/7813 ,  H01L29/0878

摘要： A double diffused field effect transistor and a method of forming the same is provided. The method begins by providing a substrate of a first conductivity type. Next, at least one dopant species, also of the first conductivity type, is introduced into a surface of the substrate so that the substrate has a nonuniform doping profile. An epitaxial layer of the first conductivity type is formed over the substrate and one or more body regions of a second conductivity type are formed within the epitaxial layer. A plurality of source regions of the first conductivity type are then formed within the body regions. Finally, a gate region is formed, which is adjacent to the body regions.