公开(公告)号：US06885593B2

公开(公告)日：2005-04-26

申请号：US10683441

申请日：2003-10-14

申请人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Takao Watanabe

发明人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Takao Watanabe

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C11/406 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C7/1039 ,  G11C7/1072

摘要： A dynamic memory requires refreshing to retain data in its memory cells. This may cause access to the dynamic memory for purposes other than refreshing (external access) and access to it for refreshing to compete with each other, resulting in a performance deterioration. According to this invention, a pipelined dynamic memory (PDRAM) is used, and the pipeline frequency (CLK) of the pipelined dynamic memory is made higher than the frequency (CLK1) of external access, and access required for refreshing is made to an unoccupied slot (a timing when any external access request is never issued) in the pipeline of the pipelined dynamic memory. This makes refreshing of the internal dynamic memory an internal operation, which eliminates the need to take refreshing into consideration at the time external access is made, leading to improvement in operating ease and speed.

摘要翻译： 动态存储器需要刷新以将数据保留在其存储单元中。 这可能导致访问动态存储器用于除了刷新（外部访问）之外的目的，并且访问它以进行刷新以相互竞争，导致性能恶化。 根据本发明，使用流水线动态存储器（PDRAM），并且使流水线动态存储器的流水线频率（CLK）高于外部访问的频率（CLK 1），并且进行刷新所需的访问 未被占用的时隙（从未发布任何外部访问请求的定时）在流水线动态存储器的流水线中。 这使得内部动态存储器的刷新成为内部操作，这消除了在外部访问时考虑到刷新的需要，从而改善了操作的容易性和速度。

公开(公告)号：US06829186B2

公开(公告)日：2004-12-07

申请号：US10606957

申请日：2003-06-27

申请人： Yusuke Kanno ,  Kiyoo Itoh

发明人： Yusuke Kanno ,  Kiyoo Itoh

IPC分类号： G11C700

CPC分类号： G11C7/18 ,  G11C11/405 ,  G11C11/4097

摘要： A semiconductor integrated circuit is disclosed, in which a memory is activated at high speed in commensurate with a high-speed logic circuit mounted with the memory in order to reduce the cost using a DRAM of a 3-transistor cell requiring no capacitor. A pair of data lines connected with a plurality of memory cells having the amplification function are set to different precharge voltage values, thereby eliminating the need of a dummy cell. The elimination of the need of the dummy cell unlike in the conventional DRAM circuit using a gain cell reduces both the required space and the production cost. A hierarchical structure of the data lines makes a high-speed operation possible. Also, a DRAM circuit can be fabricated through a fabrication process matched with an ordinary logic element.

公开(公告)号：US06715025B2

公开(公告)日：2004-03-30

申请号：US10186891

申请日：2002-07-02

申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takao Watanabe

发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takao Watanabe

IPC分类号： G06F1300

CPC分类号： G06F12/0607 ,  G06F12/0882

摘要： In an information processing apparatus involving a cache accessed by INDEX and TAG addresses, accesses to the main memory include many accesses attributable to the local character of referencing and write-back accesses attributable to the replacement of cache contents. Accordingly, high speed accessing requires efficient assignment of the two kinds of accesses to banks of the DRAM. In assigning request addresses from the CPU to different banks of the DRAM, bank addresses of the DRAM are generated by operation of the INDEX field and the TAG field so that local accesses whose INDEX varies and accesses at the time of writing back of which INDEX remains the same but TAG differs can be assigned to different banks, thereby enabling high speed accessing. Furthermore, as reading and writing at the time of writing back can be assigned to a separate bank, pseudo dual-port accessing is made possible with only one port, resulting in higher speed write-back accessing.

摘要翻译： 在涉及由INDEX和TAG地址访问的高速缓冲存储器的信息处理装置中，对主存储器的访问包括归因于替代缓存内容的引用和回写访问的本地字符的许多访问。 因此，高速存取需要对DRAM的存储体的两种访问进行有效的分配。 在将请求地址从CPU分配给DRAM的不同库时，通过INDEX字段和TAG字段的操作来生成DRAM的存储区地址，以使其INDEX变化的本地访问在写入INDEX时被保留 相同但是TAG不同可以分配给不同的存储体，从而实现高速存取。 此外，由于在回写时的读写可以分配给单独的存储区，因此只能使用一个端口进行伪双端口访问，从而实现更高速的写回访问。

公开(公告)号：US06469948B2

公开(公告)日：2002-10-22

申请号：US09885066

申请日：2001-06-21

申请人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Takao Watanabe

发明人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Takao Watanabe

IPC分类号： G11C800

CPC分类号： G11C11/406 ,  G11C7/1039 ,  G11C7/1072

摘要： A dynamic memory requires refreshing to retain data in its memory cells. This may cause access to the dynamic memory for purposes other than refreshing (external access) and access to it for refreshing to compete with each other, resulting in a performance deterioration. According to this invention, a pipelined dynamic memory. (PDRAM) is used, and the pipeline frequency (CLK) of the pipelined dynamic memory is made higher than the frequency (CLK1) of external access, and access required for refreshing is made to an unoccupied slot (a timing when any external access request is never issued) in the pipeline of the pipelined dynamic memory. This makes refreshing of the internal dynamic memory an internal operation, which eliminates the need to take refreshing into consideration at the time external access is made, leading to improvement in operating ease and speed.

摘要翻译： 动态存储器需要刷新以将数据保留在其存储单元中。 这可能导致访问动态存储器用于除了刷新（外部访问）之外的目的，并且访问它以进行刷新以相互竞争，导致性能恶化。 根据本发明，流水线动态存储器。 （PDRAM），并且使流水线动态存储器的流水线频率（CLK）高于外部访问的频率（CLK1），并且对未占用时隙进行刷新所需的访问（任何外部访问请求的定时 在流水线动态存储器的流水线中永远不会发布）。 这使得内部动态存储器的刷新成为内部操作，这消除了在外部访问时考虑到刷新的需要，从而改善了操作的容易性和速度。

公开(公告)号：US20100083011A1

公开(公告)日：2010-04-01

申请号：US12466696

申请日：2009-05-15

申请人： Masafumi ONOUCHI ,  Hiroyuki Mizuno ,  Yusuke Kanno ,  Makoto Saen

发明人： Masafumi ONOUCHI ,  Hiroyuki Mizuno ,  Yusuke Kanno ,  Makoto Saen

IPC分类号： G06F15/76 ,  G06F1/10 ,  G06F1/26 ,  G06F9/02

CPC分类号： G06F1/3203 ,  G06F1/10 ,  Y02D10/126

摘要： In a configuration provided with, for example, sixty four pieces of processor cores, an on-chip-memory, a bus commonly connected thereto, and others, the processor cores are operated by a power supply with low voltage and a clock with low frequency, and the bus is operated by a power supply with high voltage and a clock with high frequency. Each of the processor cores is provided with a bus interface and a frequency divider in order to absorb a power supply voltage difference and a frequency difference between the bus and each of them. The frequency divider generates the clock with low frequency from the clock with high frequency, and the bus interface is provided with a level shifting function, a data width converting function, a hand shaking function between the bus and the bus interface, and the like.

摘要翻译： 在具有例如六十四个处理器核心，片上存储器，与其连接的总线等的配置中，处理器核心由具有低电压的电源和具有低频率的时钟 ，总线由高电压电源和高频时钟驱动。 每个处理器内核都配有一个总线接口和一个分频器，以便吸收总线与它们中的每一个之间的电源电压差和频率差。 分频器从高频时钟产生低频时钟，总线接口提供电平转换功能，数据宽度转换功能，总线与总线接口之间的手抖功能等。

公开(公告)号：US20090027984A1

公开(公告)日：2009-01-29

申请号：US12242164

申请日：2008-09-30

申请人： HIROYUKI MIZUNO ,  Takeshi Sakata ,  Nobuhiro OODAIRA ,  Takao Watanabe ,  Yusuke Kanno

发明人： HIROYUKI MIZUNO ,  Takeshi Sakata ,  Nobuhiro OODAIRA ,  Takao Watanabe ,  Yusuke Kanno

IPC分类号： G11C7/00

CPC分类号： G11C11/4076 ,  G11C7/04 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to bit line LBL.

摘要翻译： 本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为 过程波动很大程度。 本发明提供以下典型的效果。 在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置，用于这些位线的隔离和耦合。 位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BL的最大幅度电压。 读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。 当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到位线LBL的锁存型读出放大器SA。

公开(公告)号：US07436722B2

公开(公告)日：2008-10-14

申请号：US11761642

申请日：2007-06-12

申请人： Hiroyuki Mizuno ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

发明人： Hiroyuki Mizuno ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

IPC分类号： G11C7/00

CPC分类号： G11C11/4076 ,  G11C7/04 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.

摘要翻译： 本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为 过程波动很大程度。 本发明提供以下典型的效果。 在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置以隔离和耦合这些位线。位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电 到VDL的电压。 VDL是位线BL的最大幅度电压。 读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。 当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。

公开(公告)号：US07428720B2

公开(公告)日：2008-09-23

申请号：US11797034

申请日：2007-04-30

申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Naohiko Irie

发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Naohiko Irie

IPC分类号： G06F17/50

CPC分类号： G01R31/318572 ,  G11C5/063 ,  G11C11/417 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K3/356008 ,  H03K3/35625 ,  H03K19/0016 ,  H01L2924/00

摘要： In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefor for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.

摘要翻译： 在功率关闭时保留先前数据的低功耗模式下，其返回速度增加。 虽然可以考虑使用现有的数据保持触发器，但是这不是优选的，因为它增加了诸如扩大单元大小的面积开销。 用于电源关闭的数据保持的电源线由比通常的主电源线更细的布线形成。 优选地，用于数据保持电路的电力线被认为是信号线，并通过自动放置和安装进行布线。 为此，先前通过以与现有信号线相同的方式为小区提供终端来设计用于数据保持的电力线的终端。 电池线的附加布局不再需要，这使得现有的放置和布线工具能够减少面积和设计。

公开(公告)号：US20070291564A1

公开(公告)日：2007-12-20

申请号：US11761642

申请日：2007-06-12

申请人： Hiroyuki MIZUNO ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

发明人： Hiroyuki MIZUNO ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

IPC分类号： G11C7/00

CPC分类号： G11C11/4076 ,  G11C7/04 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.

摘要翻译： 本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为 过程波动很大程度。 本发明提供以下典型的效果：位线BL与连接到存储单元的局部位线LBL之间的开关装置用于隔离和耦合这些位线位线BL被预充电到VDL / 2的电压， 而局部位线LBL被预充电到VDL的电压。 VDL是位线BLA的最大幅度电压。读出放大器SA包括包括连接到位线BL的栅极的差分MOS对的第一电路和连接到用于全幅放大的局部位线LBL的第二电路， 用于保存数据。 当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。

公开(公告)号：US07242627B2

公开(公告)日：2007-07-10

申请号：US11363085

申请日：2006-02-28

申请人： Hiroyuki Mizuno ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

发明人： Hiroyuki Mizuno ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C11/4076 ,  G11C7/04 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use latch type sense amplifier SA connected to the local bit line LBL.

摘要翻译： 本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为 过程波动很大程度。 本发明提供以下典型的效果。 在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置，用于这些位线的隔离和耦合。 位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BL的最大幅度电压。 读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。 当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。