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170 条记录 (耗时 0.027 秒)

    Self-converging bottom electrode ring
    62.
    发明授权
    Self-converging bottom electrode ring 失效
    自收敛底电极环

    公开(公告)号：US07935564B2

    公开(公告)日：2011-05-03

    申请号：US12036372

    申请日：2008-02-25

    申请人： Matthew J. Breitwisch ,  Chung H. Lam ,  Hsiang-Lan Lung

    发明人： Matthew J. Breitwisch ,  Chung H. Lam ,  Hsiang-Lan Lung

    IPC分类号： H01L47/00

    CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683 ,  Y10S438/90

    摘要： A method and memory cell including self-converged bottom electrode ring. The method includes forming a step spacer, a top insulating layer, an intermediate insulating layer, and a bottom insulating layer above a substrate. The method includes forming a step spacer within the top insulating layer and the intermediate insulating layer. The step spacer size is easily controlled. The method also includes forming a passage in the bottom insulating layer with the step spacer as a mask. The method includes forming bottom electrode ring within the passage comprising a cup-shaped outer conductive layer within the passage and forming an inner insulating layer within the cup-shaped outer conductive layer. The method including forming a phase change layer above the bottom electrode ring and a top electrode above the bottom electrode ring.

    摘要翻译： 一种包括自会聚底电极环的方法和存储单元。 该方法包括在衬底上形成台阶间隔物，顶部绝缘层，中间绝缘层和底部绝缘层。 该方法包括在顶部绝缘层和中间绝缘层内形成台阶间隔物。 台阶垫片尺寸易于控制。 该方法还包括在步骤间隔物作为掩模的底部绝缘层中形成通道。 所述方法包括在所述通道内形成底部电极环，所述通道包括所述通道内的杯形外部导电层，并且在所述杯形外部导电层内形成内部绝缘层。 该方法包括在底部电极环上方形成相变层和在底部电极环上方形成顶部电极。

    CHEMICAL MECHANICAL POLISHING STOP LAYER FOR FULLY AMORPHOUS PHASE CHANGE MEMORY PORE CELL
    63.
    发明申请
    CHEMICAL MECHANICAL POLISHING STOP LAYER FOR FULLY AMORPHOUS PHASE CHANGE MEMORY PORE CELL 有权
    化学机械抛光停止层，用于完全不相变的记忆孔细胞

    公开(公告)号：US20110049461A1

    公开(公告)日：2011-03-03

    申请号：US12550062

    申请日：2009-08-28

    申请人： Matthew J. Breitwisch ,  Chung H. Lam

    发明人： Matthew J. Breitwisch ,  Chung H. Lam

    IPC分类号： H01L45/00 ,  H01L21/20

    CPC分类号： H01L21/31144 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683 ,  H01L45/1691

    摘要： A method for fabricating a phase change memory pore cell that includes forming a bottom electrode, forming a first dielectric layer on the bottom electrode, forming a sacrificial layer on the first dielectric layer, forming an isolation layer on the sacrificial layer, and forming a second dielectric layer on the isolation layer. The method further includes forming a via overlying the bottom electrode, the via extending to the sacrificial layer, etching through the sacrificial layer to the first dielectric layer to form a pore defined extending through the sacrificial layer and the first dielectric layer, depositing phase change material on the sacrificial layer and into the pore and removing the phase change material formed outside the pore, removing the sacrificial layer to expose the pore, the pore being vertically aligned, and forming a top electrode over the pore.

    摘要翻译： 一种相变存储孔单元的制造方法，包括形成底电极，在所述底电极上形成第一电介质层，在所述第一电介质层上形成牺牲层，在所述牺牲层上形成隔离层，形成第二电介质层 隔离层上的介电层。 该方法还包括形成覆盖底部电极的通孔，延伸到牺牲层的通孔，通过牺牲层蚀刻到第一介电层，以形成限定的孔，延伸穿过牺牲层和第一介电层，沉积相变材料 在牺牲层上并进入孔中，除去形成在孔外部的相变材料，去除牺牲层以暴露孔，孔垂直排列，并在孔上形成顶电极。

    Fin-type antifuse
    64.
    发明授权
    Fin-type antifuse 有权
    翅式反熔丝

    公开(公告)号：US07691684B2

    公开(公告)日：2010-04-06

    申请号：US12183169

    申请日：2008-07-31

    申请人： Matthew J. Breitwisch ,  Chung H. Lam ,  Edward J. Nowak

    发明人： Matthew J. Breitwisch ,  Chung H. Lam ,  Edward J. Nowak

    IPC分类号： H01L21/82

    CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A method of forming an antifuse forms a material layer and then patterns the material layer into a fin. The center portion of the fin is converted into a substantially non-conductive region and the end portions of the fin into conductors. The process of converting the center portion of the fin into an insulator allows a process of heating the fin above a predetermined temperature to convert the insulator into a conductor. Thus, the fin-type structure that can be selectively converted from an insulator into a permanent conductor using a heating process.

    摘要翻译： 形成反熔丝的方法形成材料层，然后将材料层图案化成翅片。 翅片的中心部分被转换成基本上不导电的区域，并且翅片的端部变成导体。 将翅片的中心部分转换成绝缘体的过程允许将翅片加热到高于预定温度的过程，以将绝缘体转换为导体。 因此，可以使用加热工艺从绝缘体选择性地转换成永久导体的鳍式结构。

    MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION
    65.
    发明申请
    MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION 有权
    多级存储单元利用测量时间延迟作为等级定义的特征参数

    公开(公告)号：US20090073785A1

    公开(公告)日：2009-03-19

    申请号：US11857370

    申请日：2007-09-18

    申请人： Matthew J. Breitwisch ,  Chung H. Lam ,  Bipin Rajendran

    发明人： Matthew J. Breitwisch ,  Chung H. Lam ,  Bipin Rajendran

    IPC分类号： G11C7/10

    CPC分类号： G11C11/5628 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/32 ,  G11C2013/0076

    摘要： A method for operating a memory cell. Memory cells represent binary values by storing a characteristic parameter. The method of memory cell operation entails receiving a binary value to be stored by a memory cell. A determining operation determines a target discharge time corresponding to the binary value. The target discharge time being the time needed to discharge a pre-charged circuit through the said memory cell to a predetermined level. A storing operation stores a characteristic parameter in the memory cell such that an electron discharge time through an electronic circuit formed, at least partially, by the memory cell, is substantially equal to the target discharge time.

    摘要翻译： 一种操作存储单元的方法。 存储单元通过存储特征参数来表示二进制值。 存储单元操作的方法需要接收由存储器单元存储的二进制值。 确定操作确定对应于二进制值的目标放电时间。 目标放电时间是将预充电电路通过所述存储单元放电至预定水平所需的时间。 存储操作将特征参数存储在存储单元中，使得通过至少部分地由存储单元形成的电子电路的电子放电时间基本上等于目标放电时间。

    MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION
    66.
    发明申请
    MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION 有权
    多级存储单元利用测量时间延迟作为等级定义的特征参数

    公开(公告)号：US20090073784A1

    公开(公告)日：2009-03-19

    申请号：US11857356

    申请日：2007-09-18

    申请人： Matthew J. Breitwisch ,  Chung H. Lam ,  Bipin Rajendran

    发明人： Matthew J. Breitwisch ,  Chung H. Lam ,  Bipin Rajendran

    IPC分类号： G11C7/00 ,  G11C7/10

    CPC分类号： G11C11/565 ,  G11C11/5628 ,  G11C11/5678 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C16/32 ,  G11C2013/0054

    摘要： A memory array and computer program product for operating a memory cell and memory array. An embodiment of the invention entails receiving a binary value to be stored by a memory cell. A determining operation determines a target discharge time corresponding to the binary value. The target discharge time being the time needed to discharge a pre-charged circuit through the said memory cell to a predetermined level. A storing operation stores a characteristic parameter in the memory cell such that an electron discharge time through an electronic circuit formed, at least partially, by the memory cell, is substantially equal to the target discharge time.

    摘要翻译： 用于操作存储器单元和存储器阵列的存储器阵列和计算机程序产品。 本发明的实施例需要接收由存储器单元存储的二进制值。 确定操作确定对应于二进制值的目标放电时间。 目标放电时间是将预充电电路通过所述存储单元放电至预定水平所需的时间。 存储操作将特征参数存储在存储单元中，使得通过至少部分地由存储单元形成的电子电路的电子放电时间基本上等于目标放电时间。

    Isolated fully depleted silicon-on-insulator regions by selective etch
    67.
    发明授权
    Isolated fully depleted silicon-on-insulator regions by selective etch 失效
    通过选择性蚀刻隔离完全耗尽的绝缘体上硅区域

    公开(公告)号：US07190007B2

    公开(公告)日：2007-03-13

    申请号：US10710821

    申请日：2004-08-05

    申请人： Matthew J. Breitwisch ,  Chung H. Lam ,  Randy W. Mann ,  Dale W. Martin

    发明人： Matthew J. Breitwisch ,  Chung H. Lam ,  Randy W. Mann ,  Dale W. Martin

    IPC分类号： H01L29/47

    CPC分类号： H01L21/764 ,  H01L21/76283 ,  H01L21/76289 ,  H01L29/78654

    摘要： The present invention provides a method of forming an ultra-thin and uniform layer of Si including the steps of providing a substrate having semiconducting regions separated by insulating regions; implanting dopants into the substrate to provide an etch differential doped portion in the semiconducting regions underlying an upper Si-containing surface of the semiconducting regions; forming a trench in the substrate including the semiconducting regions and the insulating regions; removing the etch differential doped portion from the semiconductor regions to produce a cavity underlying the upper surface of the semiconducting regions; and filling the trench with a trench dielectric, wherein the trench dielectric material encloses the cavity underlying the upper Si-containing surface of the semiconducting regions. The upper Si-containing surface of the semiconducting regions has a uniform thickness of less than about 100 Å.

    摘要翻译： 本发明提供一种形成超薄且均匀的Si层的方法，包括以下步骤：提供具有由绝缘区分隔开的半导体区域的衬底; 将掺杂剂注入衬底中以在半导体区域的上部含Si表面下方的半导体区域中提供蚀刻差分掺杂部分; 在包括半导体区域和绝缘区域的衬底中形成沟槽; 从所述半导体区域去除所述蚀刻差分掺杂部分以在所述半导体区域的上表面下方形成空腔; 以及用沟槽电介质填充所述沟槽，其中所述沟槽电介质材料包围在所述半导体区域的所述上部含Si表面之下的空腔。 半导体区域的上部含Si表面具有小于约的均匀厚度。

    Small footprint phase change memory cell
    68.
    发明授权
    Small footprint phase change memory cell 有权
    小尺寸相变存储单元

    公开(公告)号：US08728859B2

    公开(公告)日：2014-05-20

    申请号：US12855079

    申请日：2010-08-12

    申请人： Matthew J. Breitwisch ,  Eric A. Joseph ,  Chung H. Lam ,  Hsiang-Lan Lung

    发明人： Matthew J. Breitwisch ,  Eric A. Joseph ,  Chung H. Lam ,  Hsiang-Lan Lung

    IPC分类号： H01L21/00 ,  H01L45/00

    CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675 ,  H01L45/1683 ,  H01L45/1691

    摘要： An example embodiment disclosed is a method for fabricating a phase change memory cell. The method includes forming a non-sublithographic via within an insulating substrate. The insulating substrate is embedded on the same layer as a first metalization layer (Metal 1) of a semiconductor wafer, and includes a bottom and a sidewall. A sublithographic aperture is formed through the bottom of the non-sublithographic via and extends to a buried conductive material. The sublithographic aperture is filled with a conductive non-phase change material. Furthermore, phase change material is deposited within the non-sublithographic via.

    摘要翻译： 所公开的示例性实施例是用于制造相变存储单元的方法。 该方法包括在绝缘衬底内形成非亚光刻通孔。 绝缘基板被嵌入与半导体晶片的第一金属化层（金属1）相同的层上，并且包括底部和侧壁。 通过非亚光刻通孔的底部形成亚光刻孔，并延伸到掩埋的导电材料。 亚光刻孔填充有导电非相变材料。 此外，相变材料沉积在非亚光刻通孔内。

    Chemical mechanical polishing stop layer for fully amorphous phase change memory pore cell
    69.
    发明授权
    Chemical mechanical polishing stop layer for fully amorphous phase change memory pore cell 有权
    化学机械抛光停止层，用于完全非晶相变记忆孔细胞

    公开(公告)号：US08492194B2

    公开(公告)日：2013-07-23

    申请号：US13102550

    申请日：2011-05-06

    申请人： Matthew J. Breitwisch ,  Chung H. Lam

    发明人： Matthew J. Breitwisch ,  Chung H. Lam

    IPC分类号： H01L21/06 ,  H01L21/108 ,  H01L21/44 ,  H01L21/20

    CPC分类号： H01L21/31144 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683 ,  H01L45/1691

    摘要： A method for fabricating a phase change memory pore cell that includes forming a bottom electrode, forming a dielectric layer on the bottom electrode, and forming a sacrificial layer on the dielectric layer. The method further includes selectively etching portions of the sacrificial layer and the dielectric layer to define a pore extending through the sacrificial layer and the dielectric layer, depositing phase change material on the sacrificial layer and into the pore and removing the phase change material formed outside the pore, removing the sacrificial layer to expose the pore, the pore being vertically aligned, and forming a top electrode over the pore.

    摘要翻译： 一种制造相变存储孔元电池的方法，包括形成底电极，在底电极上形成电介质层，并在电介质层上形成牺牲层。 该方法还包括选择性地蚀刻牺牲层和电介质层的部分，以限定延伸穿过牺牲层和电介质层的孔，在牺牲层上沉积相变材料并进入孔并除去形成在外部的相变材料 孔，去除牺牲层以暴露孔，孔垂直对齐，并在孔上形成顶电极。