公开(公告)号：US10949291B2

公开(公告)日：2021-03-16

申请号：US16776600

申请日：2020-01-30

Applicant: Micron Technology, Inc.

Inventor： Dheeraj Srinivasan ,  Ali Mohammadzadeh

IPC: H03M7/04 ,  H03M13/05 ,  H03M13/09 ,  G06F11/10 ,  G11C11/56 ,  G11C8/12 ,  G11C16/08 ,  G11C16/10 ,  G11C16/28 ,  H03M13/37 ,  G11C29/02

Abstract: The present disclosure relates to partially written superblock treatment. An example apparatus includes a memory device operable as a multiplane memory resource including blocks organized as superblocks. The memory device is configured to maintain, internal to the memory device, included in a status of an open superblock, a page indicator corresponding to a last written page of the open superblock. The memory device is further configured, responsive to receipt, from a controller, of a read request to a page of the open superblock, determine from page map information maintained internal to the memory device and from the indicator of the last written page, which of a number of different read trim sets to use to read the page of the open superblock corresponding to the read request.

公开(公告)号：US10762974B2

公开(公告)日：2020-09-01

申请号：US16430086

申请日：2019-06-03

Applicant: Micron Technology, Inc.

Inventor： Aliasgar S. Madraswala ,  Kristopher H. Gaewsky ,  Naveen Vittal Prabhu ,  Purval S. Sule ,  Trupti Bemalkhedkar ,  Nehul N. Tailor ,  Quan H. Ngo ,  Dheeraj Srinivasan

IPC: G11C16/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/04

Abstract: Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US10552254B2

公开(公告)日：2020-02-04

申请号：US15677736

申请日：2017-08-15

Applicant: Micron Technology, Inc.

Inventor： Dheeraj Srinivasan ,  Ali Mohammadzadeh

IPC: G06F11/10 ,  G11C11/56 ,  H03M13/37

Abstract: The present disclosure relates to partially written superblock treatment. An example apparatus includes a memory device operable as a multiplane memory resource including blocks organized as superblocks. The memory device is configured to maintain, internal to the memory device, included in a status of an open superblock, a page indicator corresponding to a last written page of the open superblock. The memory device is further configured, responsive to receipt, from a controller, of a read request to a page of the open superblock, determine from page map information maintained internal to the memory device and from the indicator of the last written page, which of a number of different read trim sets to use to read the page of the open superblock corresponding to the read request.

公开(公告)号：US20190355422A1

公开(公告)日：2019-11-21

申请号：US16530100

申请日：2019-08-02

Applicant: Micron Technology, Inc.

Inventor： Dheeraj Srinivasan ,  Jeffrey M. Tsai ,  Ali Mohammadzadeh ,  Terry M. Grunzke

IPC: G11C16/08 ,  G11C8/08 ,  G11C16/12 ,  G06F3/06

Abstract: The present disclosure relates to apparatuses and methods for an automated dynamic word line start voltage. An example apparatus includes a controller and a memory device. The memory device is configured to maintain, internal to the memory device, a status of a number of open blocks in the memory device. The status can include a programming operation being initiated in the respective number of open blocks. Responsive to receipt of, from the controller, a request to direct initiation of the programming operation to a word line, determine a group of memory cells associated with the word line that programs first relative to other groups of memory cells associated with the word line and maintain, included in the status of an open block, a voltage at which the group of memory cells is the first group to program.

公开(公告)号：US10354738B2

公开(公告)日：2019-07-16

申请号：US15717554

申请日：2017-09-27

Applicant: Micron Technology, Inc.

Inventor： Aliasgar S. Madraswala ,  Kristopher H. Gaewsky ,  Naveen Vittal Prabhu ,  Purval S. Sule ,  Trupti Bemalkhedkar ,  Nehul N. Tailor ,  Quan H. Ngo ,  Dheeraj Srinivasan

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04

Abstract: Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20190065095A1

公开(公告)日：2019-02-28

申请号：US16178366

申请日：2018-11-01

Applicant: Micron Technology, Inc.

Inventor： Dheeraj Srinivasan ,  Ali Mohammadzadeh

IPC: G06F3/06 ,  G11C16/10 ,  G11C11/56 ,  G06F12/0811

CPC classification number: G06F3/0638 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0673 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0868 ,  G06F2212/1024 ,  G06F2212/214 ,  G06F2212/7203 ,  G06F2212/7208 ,  G11C11/5628 ,  G11C16/10

Abstract: Apparatuses and methods for performing buffer operations in memory are provided. An example apparatus can include an array of memory cells, a page buffer, and a controller. The page buffer can be configured to store a number of pages of data in respective caches of the page buffer. The controller can be configured to program the number of pages of data to a first group of cells in the array. The programming operation can include programming the first group of cells to target states encoded with respective data patterns. The programming operation can include incrementally releasing a first of the respective caches of the page buffer responsive to completing programming of cells programmed to a particular first one of the target states.