公开(公告)号：US20230315569A1

公开(公告)日：2023-10-05

申请号：US18206398

申请日：2023-06-06

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Nadav Grosz ,  Lance W. Dover ,  Yoav Weinberg

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F12/02 ,  G06F13/42 ,  G06F12/14

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/3037 ,  G06F12/0246 ,  G06F13/4221 ,  G06F12/1408 ,  G06F2212/7201

Abstract: A storage device includes a memory storage region and a controller having a processor. The processor retrieves user data from the memory storage region using a physical block address corresponding to a logical block address (LBA), in response to a read command. The retrieved user data includes a first hash received through a host interface in a prior host data transmission. The processor further performs error correction on the user data to generate error-corrected user data. The processor further causes a cryptographic engine to produce a second hash of the error-corrected user data. The first hash is compared to the second hash associated with the error-corrected user data to determine a match result. A notification is generated in response to the match result.

公开(公告)号：US11748005B2

公开(公告)日：2023-09-05

申请号：US16989599

申请日：2020-08-10

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz ,  Qing Liang

IPC: G06F3/06 ,  G06F1/3234

CPC classification number: G06F3/0634 ,  G06F1/3275 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0685

Abstract: Methods, systems, and devices for transferring memory system data to an auxiliary array are described. A memory system may be configured for transferring information between a relatively volatile memory array and a relatively non-volatile memory array in response to transitions between various operating modes, such as operating modes associated with different operating power levels. For example, before entering a reduced power mode, the memory system may identify information stored in a volatile memory array and transfer the identified information to an auxiliary, non-volatile memory array. Such information may be returned to the relatively volatile memory array to support memory system operation after exiting the reduced power mode. In some examples, such information exchanged between the memory system and the host system may be associated with a processing capability of the memory system, and the described operations may be referred to as suspending memory system processing information to an auxiliary array.

公开(公告)号：US11720359B2

公开(公告)日：2023-08-08

申请号：US17558140

申请日：2021-12-21

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Nadav Grosz

IPC: G06F12/00 ,  G06F9/30 ,  G06F9/48 ,  G06F3/06 ,  G06F12/1009

CPC classification number: G06F9/30047 ,  G06F3/0613 ,  G06F3/0617 ,  G06F3/0646 ,  G06F3/0659 ,  G06F3/0679 ,  G06F9/4806 ,  G06F12/1009 ,  G06F2212/7201

Abstract: Devices and techniques are disclosed herein for more efficiently exchanging large amounts of data between a host and a storage system. In an example, a read command can optionally include a read-type indicator. The read-type indicator can allow for exchange of a large amount of data between the host and the storage system using a single read command.

公开(公告)号：US11720261B2

公开(公告)日：2023-08-08

申请号：US16989596

申请日：2020-08-10

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Nadav Grosz ,  Jonathan S. Parry ,  Deping He

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0623 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for transferring memory system data to a host system are described. A system may be configured for transferring information between a memory system and a host system in response to transitions between various operating modes, such as operating modes associated with different operating power levels. For example, before entering a reduced power mode, the memory system may identify information stored in a volatile memory array and transmit the identified information to the host system. Such information transmitted to the host system may be returned to the memory system to support memory system operation after exiting the reduced power mode. In some examples, such information exchanged between the memory system and the host system may be associated with a processing capability of the memory system, and the described operations may be referred to as suspending memory system processing information to a host system.

公开(公告)号：US20230168835A1

公开(公告)日：2023-06-01

申请号：US17994543

申请日：2022-11-28

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz

IPC: G06F3/06 ,  H04L9/32

CPC classification number: G06F3/0652 ,  H04L9/32 ,  G06F3/0679 ,  G06F3/0623

Abstract: A memory device comprises a memory array including memory cells, a communication interface to a host device, and a memory control unit operatively coupled to the memory array and the communication interface. The memory control unit is configured to encrypt write data received via the communication interface to produce encrypted data, program a portion of the memory cells of the memory array with the encrypted data, read the encrypted data from the portion of the memory cells in response to a memory read request, decrypt the read encrypted data to produce read decrypted data only for portions of the read encrypted data not stored in purged regions of the memory array.

公开(公告)号：US20220327014A1

公开(公告)日：2022-10-13

申请号：US17853337

申请日：2022-06-29

Applicant: Micron Technology, Inc.

Inventor： Jonathan Scott Parry ,  Nadav Grosz

IPC: G06F11/07 ,  G06F9/445 ,  G06F1/3287 ,  G06F1/3225 ,  G06F1/3228 ,  G06F1/3237

Abstract: Apparatus and methods are disclosed, including determining whether firmware has been successfully loaded and whether the firmware version is valid and operable, and if the firmware has not been successfully loaded or the firmware is not valid and operable, tracking a number of unsuccessful attempts to load the firmware or an elapsed time for unsuccessful attempts to load the firmware, and entering a memory device into a reduced-power state if either the number of unsuccessful attempts or the elapsed time has reached a programmable threshold.

公开(公告)号：US20220300061A1

公开(公告)日：2022-09-22

申请号：US17648394

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Nadav Grosz ,  Jonathan S. Parry

IPC: G06F1/3234 ,  G06F1/3287

Abstract: Methods, systems, and devices for shallow hibernate power state are described. A memory system may include a memory array and a controller. The memory system may transition from a first power state having a first current to a second power state having a second current less than the first current, where the first power state is associated with executing received commands and the second power state is associated with deactivating one or more components of the memory array. The memory system may initiate a timer after transitioning from the first power state to the second power state. The memory system may determine the timer satisfies a threshold and transition from the second power state to a third power state having a third current less than the second current based on the timer satisfying the threshold.

公开(公告)号：US20220147281A1

公开(公告)日：2022-05-12

申请号：US17582480

申请日：2022-01-24

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Nadav Grosz

IPC: G06F3/06

Abstract: Devices and techniques are disclosed herein for more efficiently exchanging large amounts of data between a host and a storage system. In an example, a large read operation can include receiving a pre-fetch command, a parameter list and a read command at a storage system. In certain examples, the pre-fetch command can provide an indication of the length of the parameter list, and the parameter list can provide location identifiers of the storage system from which the read command can sense the read data.

公开(公告)号：US20220027269A1

公开(公告)日：2022-01-27

申请号：US17493431

申请日：2021-10-04

Applicant: Micron Technology, Inc.

Inventor： Jonathan Scott Parry ,  Nadav Grosz

IPC: G06F12/0804 ,  G06F3/06 ,  G06F12/02 ,  G06F12/10

Abstract: Devices and techniques for logical-to-physical (L2P) map (e.g., table) synchronization in a managed memory device are described herein. For example, plaintext portion of an L2P map may he updated in a managed memory device. In response to updating the plaintext portion of the L2P map, the updated portion can be obfuscated to create an obfuscated version of the updated portion of the L2P map. Both the updated portion and the obfuscated version of the updated portion can be saved in storage of the memory device. When a request from a host for the updated portion of the L2P map is received, the memory device can provide the obfuscated version of the portion from the storage.

公开(公告)号：US11231928B2

公开(公告)日：2022-01-25

申请号：US16592500

申请日：2019-10-03

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Nadav Grosz

IPC: G06F12/00 ,  G06F9/30 ,  G06F9/48 ,  G06F3/06 ,  G06F12/1009

Abstract: Devices and techniques are disclosed herein for more efficiently exchanging large amounts of data between a host and a storage system. In an example, a large read operation can include receiving a pre-fetch command, a parameter list and a read command at a storage system. In certain examples, the pre-fetch command can provide an indication of the length of the parameter list, and the parameter list can provide location identifiers of the storage system from which the read command can sense the read data.