公开(公告)号：US11956955B2

公开(公告)日：2024-04-09

申请号：US17150322

申请日：2021-01-15

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Nancy M. Lomeli

IPC: H10B43/27 ,  H01L21/225 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L21/2254 ,  H10B41/27

Abstract: A liner is formed laterally-outside of individual channel-material strings in one of first tiers and in one of second tiers. The liners are isotropically etched to form void-spaces in the one second tier above the one first tier. Individual of the void-spaces are laterally-between the individual channel-material strings and the second-tier material in the one second tier. Conductively-doped semiconductive material is formed against sidewalls of the channel material of the channel-material strings in the one first tier and that extends upwardly into the void-spaces in the one second tier. The conductively-doped semiconductive material is heated to diffuse conductivity-increasing dopants therein from the void-spaces laterally into the channel material laterally there-adjacent and upwardly into the channel material that is above the void-spaces.

公开(公告)号：US11889696B2

公开(公告)日：2024-01-30

申请号：US17567297

申请日：2022-01-03

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Nancy M. Lomeli

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material-string structures of memory cells extend through the insulative tiers and the conductive tiers. The channel-material-string structures individually comprise an upper portion above and joined with a lower portion. Individual of the channel-material-string structures comprise at least one external jog surface in a vertical cross-section where the upper and lower portions join. Other embodiments, including method are disclosed.

公开(公告)号：US20230247828A1

公开(公告)日：2023-08-03

申请号：US18133075

申请日：2023-04-11

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Nancy M. Lomeli

IPC: H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory array comprises a conductor tier comprising upper conductor material directly above and directly electrically coupled to lower conductor material. The upper and lower conductor materials comprise different compositions relative one another. Laterally-spaced memory blocks individually comprising a vertical stack comprise alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers and through the upper conductor material into the lower conductor material. The channel material of the channel-material strings is directly electrically coupled to the upper and lower conductor materials of the conductor tier. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. Other embodiments, including method, are disclosed.

公开(公告)号：US11706925B2

公开(公告)日：2023-07-18

申请号：US18053134

申请日：2022-11-07

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Nancy M. Lomeli ,  Justin B. Dorhout ,  Damir Fazil

IPC: H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H01L21/311 ,  H01L21/02

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

Abstract: Device, systems, and structures include a stack of vertically-alternating tiers of materials arranged in one or more decks of tiers. A channel opening, in which a channel pillar may be formed, extends through the stack. The pillar includes a “shoulder portion” extending laterally into an “undercut portion” of the channel opening, which undercut portion is defined along at least a lower tier of at least one of the decks of the stack.

公开(公告)号：US20230207469A1

公开(公告)日：2023-06-29

申请号：US17582280

申请日：2022-01-24

Applicant: Micron Technology, Inc.

Inventor： Damir Fazil ,  Indra V. Chary ,  Nancy M. Lomeli ,  Rajasekhar Venigalla

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: A memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. A through-array-via (TAV) region comprises TAV constructions that individually extend through the insulative tiers and the conductive tiers into the conductor tier. Individual of the TAV constructions comprise an upper portion directly above and joined with a lower portion. The individual TAV constructions comprise at least one external jog surface in a vertical cross-section where the upper and lower portions join. Other embodiments, including method, are disclosed.

公开(公告)号：US11690234B2

公开(公告)日：2023-06-27

申请号：US17652346

申请日：2022-02-24

Applicant: Micron Technology, Inc.

Inventor： Bo Zhao ,  Nancy M. Lomeli ,  Lifang Xu ,  Adam L. Olson

IPC: H01L27/00 ,  H01L21/8229 ,  H01L21/768 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11578

CPC classification number: H01L21/8229 ,  H01L21/76822 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L21/76877

Abstract: A microelectronic device comprises a microelectronic device structure having a memory array region and a staircase region. The microelectronic device structure comprises a stack structure having tiers each comprising a conductive structure and an insulative structure; staircase structures confined within the staircase region and having steps comprising edges of the tiers of the stack structure within the deck and the additional deck; and semiconductive pillar structures confined within the memory array region and extending through the stack structures. The stack structure comprises a deck comprising a group of the tiers; an additional deck overlying the deck and comprising an additional group of the tiers; and an interdeck section between the deck and the additional deck and comprising a dielectric structure confined within the memory array region, and another group of the tiers within vertical boundaries of the dielectric structure and confined within the staircase region.

公开(公告)号：US20230171960A1

公开(公告)日：2023-06-01

申请号：US18096264

申请日：2023-01-12

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jordan D. Greenlee ,  Nancy M. Lomeli ,  Alyssa N. Scarbrough

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Dummy pillars extend through the insulative tiers and the conductive tiers. A lowest of the conductive tiers comprises conducting material and dummy-region material that is aside and of different composition from that of the conducting material. The channel-material strings extend through the conducting material of the lowest conductive tier. The dummy pillars extend through the dummy-region material of the lowest conductive tier. Other embodiments, including method, are disclosed.

公开(公告)号：US11581330B2

公开(公告)日：2023-02-14

申请号：US17091668

申请日：2020-11-06

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jordan D. Greenlee ,  Nancy M. Lomeli ,  Alyssa N. Scarbrough

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11565

Abstract: A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Dummy pillars extend through the insulative tiers and the conductive tiers. A lowest of the conductive tiers comprises conducting material and dummy-region material that is aside and of different composition from that of the conducting material. The channel-material strings extend through the conducting material of the lowest conductive tier. The dummy pillars extend through the dummy-region material of the lowest conductive tier. Other embodiments, including method, are disclosed.

公开(公告)号：US11557597B2

公开(公告)日：2023-01-17

申请号：US16807573

申请日：2020-03-03

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Nancy M. Lomeli

IPC: H01L27/11 ,  H01L27/11556 ,  H01L21/768 ,  G11C5/02 ,  G11C5/06 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The conductive tiers comprise metal along sides of the memory blocks. Silicon is formed between the memory blocks over the metal of the conductive tiers. The silicon and the metal react to form metal silicide therefrom that is directly against and longitudinally-along the metal of individual of the conductive tiers. After the reacting, unreacted of the silicon is removed from between the memory blocks and intervening material is formed between and longitudinally-along the memory blocks. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US11495617B2

公开(公告)日：2022-11-08

申请号：US17032384

申请日：2020-09-25

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Nancy M. Lomeli ,  Justin B. Dorhout ,  Damir Fazil

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/66 ,  H01L21/311 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11573 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11556

Abstract: Device, systems, and structures include a stack of vertically-alternating tiers of materials arranged in one or more decks of tiers. A channel opening, in which a channel pillar may be formed, extends through the stack. The pillar includes a “shoulder portion” extending laterally into an “undercut portion” of the channel opening, which undercut portion is defined along at least a lower tier of at least one of the decks of the stack.