公开(公告)号：US10943624B1

公开(公告)日：2021-03-09

申请号：US16541940

申请日：2019-08-15

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner

IPC: G11C7/02 ,  G11C7/08 ,  G11C7/12 ,  G11C8/08

Abstract: Apparatuses and methods can be related to countering noise at a memory array. Countering noise can include enable switches to connect third digit lines of the first array adjacent to the respective first digit lines to fourth digit lines of the second array adjacent to the reference digit lines such that the reference digit lines experience a same amount of digit line coupling noise as the first digit lines experience.

公开(公告)号：US20210050038A1

公开(公告)日：2021-02-18

申请号：US16541940

申请日：2019-08-15

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner

IPC: G11C7/02 ,  G11C7/08 ,  G11C7/12 ,  G11C8/08

Abstract: Apparatuses and methods can be related to countering noise at a memory array. Countering noise can include enable switches to connect third digit lines of the first array adjacent to the respective first digit lines to fourth digit lines of the second array adjacent to the reference digit lines such that the reference digit lines experience a same amount of digit line coupling noise as the first digit lines experience.

公开(公告)号：US20210028308A1

公开(公告)日：2021-01-28

申请号：US16522390

申请日：2019-07-25

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Steve V. Cole ,  Scott J. Derner ,  Toby D. Robbs

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/108 ,  H01L27/11587 ,  G11C11/22 ,  G11C11/4091

Abstract: An apparatus, such as a memory array, can have a memory cell coupled to a first digit line (e.g., a local digit line) at a first level. A second digit line (e.g., hierarchical digit line) at a second level can be coupled to a main sense amplifier. A charge sharing device at a third level between the first and second levels can be coupled to the first digit line and to a connector. A vertical transistor at the third level can be coupled between the first digit line and the connector. A contact can be coupled between the connector and the second digit line.

公开(公告)号：US10885964B2

公开(公告)日：2021-01-05

申请号：US16569646

申请日：2019-09-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Scott J. Derner ,  Christopher J. Kawamura

IPC: G11C11/22 ,  H01L27/11514 ,  H01L27/11509

Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. The apparatus further includes a first digit line and a first selection component configured to couple the first plate to the first digit line, and also includes a second digit line and a second selection component configured to couple the second plate to the second digit line.

公开(公告)号：US20200328220A1

公开(公告)日：2020-10-15

申请号：US16379365

申请日：2019-04-09

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: H01L27/11507 ,  H01L29/78 ,  H01L29/08 ,  H01L23/528 ,  H01L27/108 ,  H01L27/11514

Abstract: Some embodiments include an integrated assembly. The integrated assembly has a first transistor with a horizontally-extending channel region between a first source/drain region and a second source/drain region; has a second transistor with a vertically-extending channel region between a third source/drain region and a fourth source/drain region; and has a capacitor between the first and second transistors. The capacitor has a first electrode, a second electrode, and an insulative material between the first and second electrodes. The first electrode is electrically connected with the first source/drain region, and the second electrode is electrically connected with the third source/drain region. A digit line is electrically connected with the second source/drain region. A conductive structure is electrically connected with the fourth source/drain region.

公开(公告)号：US20200234754A1

公开(公告)日：2020-07-23

申请号：US16838618

申请日：2020-04-02

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/408 ,  H01L29/78 ,  H01L49/02 ,  H01L27/108 ,  H01L27/02 ,  H01L23/528 ,  G11C11/405 ,  G11C11/404 ,  G11C11/4097

Abstract: Some embodiments include an integrated memory assembly having a first memory array deck over a second memory array deck. A first series of conductive lines extends across the first memory array deck, and a second series of conductive lines extends across the second memory array deck. A first conductive line of the first series and a first conductive line of the second series are coupled with a first component through a first conductive path. A second conductive line of the first series and a second conductive line of the second series are coupled with a second component through a second conductive path. The first and second conductive lines of the first series extend through first isolation circuitry to the first and second conductive paths, respectively; and the first and second conductive lines of the second series extend through second isolation circuitry to the first and second conductive paths, respectively.

公开(公告)号：US20200082870A1

公开(公告)日：2020-03-12

申请号：US16125326

申请日：2018-09-07

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/4091 ,  G11C11/56 ,  G11C11/4094

Abstract: An electronic device includes: a memory cell configured to store electric charge for representing a data value, wherein the memory cell is configured to store two or more levels of the electric charge corresponding to different data values; a preamplifier operably coupled to the memory cell, the preamplifier having a common source and configured to generate an amplified signal based on amplifying a difference in the two or more levels of the stored electric charge; and a sense amplifier operably coupled to the preamplifier, the sense amplifier configured to further process the amplified signal for determining the data value stored in the memory cell.

公开(公告)号：US20190279704A1

公开(公告)日：2019-09-12

申请号：US16235163

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Christopher J. Kawamura

IPC: G11C11/4074 ,  G06F3/06

Abstract: An example apparatus includes an array of memory cells coupled to an array power supply and a controller. The controller may be configured to cause a data value to be stored in at least one memory cell of the array of memory cells while the array of memory cells is operating in a first power state and a determination to be made that a change in a power status to a computing system coupled to the array of memory cells has occurred, wherein the change in the power status of the computing system is characterized by the computing device operating in a reduced power state. Responsive to the determination, the controller may be configured to cause the array power supply to be disabled to operate the array of memory cells in a second power state.

公开(公告)号：US10354712B2

公开(公告)日：2019-07-16

申请号：US16104709

申请日：2018-08-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Scott J. Derner ,  Christopher J. Kawamura

IPC: G11C11/22 ,  H01L27/11502 ,  H01L49/02 ,  H01L27/11507 ,  H01L27/11514

Abstract: Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two capacitors. Another example ferroelectric memory cell includes four transistors and two capacitors.

公开(公告)号：US10339985B2

公开(公告)日：2019-07-02

申请号：US16007022

申请日：2018-06-13

Applicant: Micron Technology, Inc.

Inventor： Charles L. Ingalls ,  Scott J. Derner

IPC: G11C7/06 ,  G11C7/22 ,  H01L29/66 ,  H01L27/108 ,  H01L27/06 ,  H01L27/092 ,  H01L21/822 ,  H01L21/8238

Abstract: A sense amplifier construction comprises a first n-type transistor and a second n-type transistor above the first n-type transistor. A third p-type transistor is included and a fourth p-type transistor is above the third p-type transistor. A lower voltage activation line is electrically coupled to n-type source/drain regions that are elevationally between respective gates of the first and second n-type transistors. A higher voltage activation line is electrically coupled to p-type source/drain regions that are elevationally between respective gates of the third and fourth p-type transistors.