公开(公告)号：US20080218192A1

公开(公告)日：2008-09-11

申请号：US11810951

申请日：2007-06-06

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R35/00

CPC classification number: G01R31/286

Abstract: A translated wafer stand-in tester (TWST), being a hybrid apparatus capable of emulating the form factor and some or all behaviors of a translated wafer under test, which is operable to store, quantify, encode and convey, either directly or remotely, data from a testing system, including but not limited to pad pressure, electrical contact and temperature. The TWST may include several stacked and attached layers,, at least one internal layer including electronic components operable to interact with a test system.

Abstract translation: 一种翻译的晶片待机测试仪（TWST），它是能够模拟被测翻译的晶片的形状因子和一些或所有行为的混合设备，其可操作以直接或远程存储，量化，编码和传送， 来自测试系统的数据，包括但不限于焊盘压力，电接触和温度。 TWST可以包括几个堆叠和连接的层，至少一个内部层，包括可操作以与测试系统相互作用的电子部件。

公开(公告)号：US06878901B2

公开(公告)日：2005-04-12

申请号：US10850021

申请日：2004-05-19

Applicant: Morgan T. Johnson ,  William A. Miller

Inventor： Morgan T. Johnson ,  William A. Miller

IPC: B23K26/073 ,  B23K26/38 ,  H05K1/00 ,  H05K1/02 ,  H05K1/16 ,  H05K3/00 ,  H05K3/02 ,  B23K26/00 ,  B23K26/14

CPC classification number: B23K26/073 ,  B23K26/382 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/12 ,  B23K2103/172 ,  B23K2103/42 ,  B23K2103/50 ,  H05K1/0269 ,  H05K1/0393 ,  H05K1/165 ,  H05K3/0032 ,  H05K3/0052 ,  H05K3/027 ,  H05K2201/09063 ,  H05K2201/0909 ,  H05K2201/09918

Abstract: A unified process of making an electrical structure includes performing a plurality of laser etching operations on a workpiece, without removing the workpiece from a laser processing system. The workpiece includes a conductive material disposed on an electrically insulating substrate, and the plurality of laser etching operations include, but are not limited to, two or more of forming a fiducial, forming thick metal traces separated by high aspect ratio spaces, cutting an alignment hole, cutting a folding line, and singulating the electrical structure. In another aspect of the invention, a database is prepared, and communicatively coupled to the laser processing system to provide control signals that direct a portion of the plurality of operations of the laser processing system, wherein each plurality of etching operations is defined with respect to a common coordinate system.

Abstract translation: 制造电气结构的统一过程包括在工件上执行多个激光蚀刻操作，而不从激光处理系统移除工件。 工件包括设置在电绝缘基板上的导电材料，并且多个激光蚀刻操作包括但不限于形成基准，形成由高纵横比空间分开的厚金属迹线的两个或更多个，切割对准 孔，切割折叠线，并分割电气结构。 在本发明的另一方面中，准备数据库，并且通信地耦合到激光处理系统以提供控制信号，该控制信号指导激光处理系统的多个操作的一部分，其中对于多个蚀刻操作相对于 一个共同的坐标系。

公开(公告)号：US06737879B2

公开(公告)日：2004-05-18

申请号：US10176571

申请日：2002-06-21

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: G01R3102

CPC classification number: G01R1/07314

Abstract: Methods and apparatus are provided for I/O pads of unsingulated integrated circuits, to be connected to electrical equipment. A translator plate is interposed between a wafer and tester. The translator plate includes a substrate having two major opposing surfaces, each surface having terminals disposed thereon, and electrical pathways disposed through the substrate to provide for electrical continuity between at least one terminal on a first surface and at least one terminal on the second surface. The translator plate, when interposed between wafer and tester, makes electrical contact with one or more I/O pads of a plurality of integrated circuits on the wafer, providing an electrical pathway therethrough. An anisotropic conductor is disposed between the wafer and the translator plate. A vibratory mechanism, oriented to provide substantially horizontal vibratory motion to the wafer, may be coupled to the wafer to assist disposing the translator plate and anisotropic conductor over the wafer.

公开(公告)号：US5937515A

公开(公告)日：1999-08-17

申请号：US971758

申请日：1997-11-17

Applicant: Morgan T. Johnson

Inventor： Morgan T. Johnson

IPC: H01L21/66 ,  H01L23/538 ,  H05K1/00 ,  H05K1/03 ,  H05K3/32 ,  H05K3/36 ,  H05K3/46

CPC classification number: H01L23/5382 ,  H01L22/22 ,  H05K1/0287 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0298 ,  H05K1/0306 ,  H05K2203/061 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49222

Abstract: A method of manufacturing electronic circuitry and the resulting hardware is described in which a conduction plate is formed achieving separate electrical conducting paths for application specific signals is engaged with an electronic circuit package containing a wide range of elements including one or more integrated circuits, chip packages, multichip modules printed circuit boards and cables. One or more of these elements are assembled into the circuit package where all or a major portion of the element conductors are routed to terminals positioned for electrical connection between the circuit apparatus and the electrical conduction plate. The conduction plate completes the electrical interconnection of the circuit package by providing the application specific conduction paths, using various techniques for creating electrical conduction, such as severing segments of a generalized conductive grid to establish desired conduction paths. The conduction plate, being separate and separable from the circuit package, enables separate design, manufacture, testing and repair of the circuit package and the conduction plate before or following final assembly of the conduction plate and circuit package. Intermediate conduction plate structures may be used to test the devices and the circuit package before final assembly, and the operational conduction plate customized to avoid defects located in the test procedure. Very substantially increased size and capacity of computers and related devices can be achieved in the same or smaller footprint using this invention.

Abstract translation: 描述了一种制造电子电路的方法和所得到的硬件，其中形成导电板，实现单独的导电路径，用于应用特定信号与包含宽范围元件的电子电路封装（包括一个或多个集成电路，芯片封装 ，多芯片模块印刷电路板和电缆。 这些元件中的一个或多个被组装到电路封装中，其中元件导体的所有或大部分被路由到定位用于电路设备和导电板之间的电连接的端子。 导电板通过提供施加特定的导电路径来完成电路封装的电互连，使用各种用于产生导电的技术，例如切断广义导电栅格的段以建立所需的传导路径。 导电板与电路封装分离并可分离，可以在导电板和电路封装的最终组装之前或之后分离设计，制造，测试和修复电路封装和导电板。 中间导电板结构可用于在最终组装之前测试器件和电路封装，并且定制操作导电板以避免位于测试程序中的缺陷。 使用本发明可以在相同或更小的占地面积中实现计算机和相关设备的大大增加的尺寸和容量。