Hot-carrier-based nonvolatile memory utilizing differing transistor structures
    61.
    发明授权
    Hot-carrier-based nonvolatile memory utilizing differing transistor structures 有权
    采用不同晶体管结构的基于热载波的非易失性存储器

    公开(公告)号:US07342821B1

    公开(公告)日:2008-03-11

    申请号:US11518066

    申请日:2006-09-08

    申请人: Kenji Noda

    发明人: Kenji Noda

    IPC分类号: G11C11/00

    摘要: A memory circuit includes a latch having a first node and a second node, a first MIS transistor operable to couple between the first node and a predetermined node, a second MIS transistor operable to couple between the second node and the predetermined node, and a control circuit configured to subject one of the first MIS transistor and the second MIS transistor to bias conditions that cause a lingering change in transistor characteristics thereof, wherein the MIS transistors of the latch have a lightly-doped-drain structure that includes first diffusion regions having a first impurity concentration and second diffusion regions having a second impurity concentration smaller than the first impurity concentration, and each of the first MIS transistor and the second MIS transistor has a doped diffusion region closest to a conduction channel with an impurity concentration different from the second impurity concentration.

    摘要翻译: 存储器电路包括具有第一节点和第二节点的锁存器,可操作以在第一节点和预定节点之间耦合的第一MIS晶体管,可操作以在第二节点和预定节点之间耦合的第二MIS晶体管,以及控制器 电路,被配置为使所述第一MIS晶体管和所述第二MIS晶体管中的一个偏置导致其晶体管特性的延迟变化的条件,其中所述锁存器的所述MIS晶体管具有轻掺杂漏极结构,所述轻掺杂漏极结构包括具有 第一杂质浓度和第二杂质浓度小于第一杂质浓度的第二扩散区,并且第一MIS晶体管和第二MIS晶体管中的每一个具有最靠近导电沟道的掺杂扩散区,杂质浓度不同于第二杂质浓度 浓度。

    Nonvolatile memory device with test mechanism
    62.
    发明申请
    Nonvolatile memory device with test mechanism 有权
    具有测试机制的非易失性存储器件

    公开(公告)号:US20070253263A1

    公开(公告)日:2007-11-01

    申请号:US11413987

    申请日:2006-04-28

    申请人: Kenji Noda

    发明人: Kenji Noda

    IPC分类号: G11C29/00

    摘要: A nonvolatile semiconductor memory device includes a memory cell having a MIS transistor configured to experience an irreversible change in transistor characteristics thereof to store data as the irreversible change, the MIS transistor having a gate node coupled to a word selecting line and a source/drain node coupled to a bit line, and the MIS transistor becoming conductive in response to a first state of the word selecting line and becoming nonconductive in response to a second state of the word selecting line, and a test circuit coupled to the bit line to sense a current running through the MIS transistor, the test circuit configured to indicate error in response to either a detection of presence of the current when the word selecting line is in the second state or a detection of absence of the current when the word selecting line is in the first state.

    摘要翻译: 非易失性半导体存储器件包括具有MIS晶体管的存储单元,其被配置为经历其晶体管特性的不可逆变化以将数据存储为不可逆变化,所述MIS晶体管具有耦合到字选择线和源极/漏极节点 耦合到位线,并且所述MIS晶体管响应于所述字选择线的第一状态变为导通,并且响应于所述字选择线的第二状态变为不导通,以及耦合到所述位线以感测 电流流过MIS晶体管,测试电路被配置为响应于当字选择线处于第二状态时检测到电流的存在或者当字选择线处于第二状态时检测到电流的错误 第一个状态。

    Gas supplying apparatus, control method of the same, gas supplying system, and endoscope system
    63.
    发明申请
    Gas supplying apparatus, control method of the same, gas supplying system, and endoscope system 审中-公开
    供气装置,其控制方法,供气系统和内窥镜系统

    公开(公告)号:US20070244363A1

    公开(公告)日:2007-10-18

    申请号:US11818158

    申请日:2007-06-13

    IPC分类号: A61B1/12 A61M37/00 A61B1/00

    摘要: A gas supplying apparatus according to the present invention includes a switching unit, which is connected to a gas supplying channel of an endoscope, configured to supply gas to the body cavity of a patient via the gas supplying channel, and switches to a state of supplying gas to the gas supplying channel or a state of stopping supply of gas, a time measuring unit configured to measure gas supply time, and a control unit, which is electrically connected to the time measuring unit, configured to control the switching unit, wherein the control unit controls the switching unit to make the gas supply to the gas supplying channel, and then controls the switching unit to switch from a state of supplying the gas to the gas supplying channel to a state of stopping supply of the gas when gas supply time by the time measuring unit is inputted, and the gas supply time measured by the time measuring unit reaches predetermined setting time set beforehand.

    摘要翻译: 根据本发明的气体供给装置包括:开关单元,其连接到内窥镜的气体供给通道,构造成经由气体供给通道向患者的体腔供给气体,并切换到供给状态 气体供给通道或停止供给气体的状态,被配置为测量供气时间的时间测量单元以及与时间测量单元电气连接的控制单元,该控制单元被配置为控制切换单元,其中, 控制单元控制切换单元使得气体供应到气体供应通道,然后控制切换单元从气体供应通道的供应状态切换到气体供应时间的停止供应状态 由时间测量单元输入,并且由时间测量单元测量的气体供应时间达到预先设定的预定设定时间。

    Nonvolatile memory utilizing asymmetric characteristics of hot-carrier effect
    64.
    发明申请
    Nonvolatile memory utilizing asymmetric characteristics of hot-carrier effect 有权
    非易失性存储器利用热载体效应的不对称特性

    公开(公告)号:US20070206413A1

    公开(公告)日:2007-09-06

    申请号:US11367952

    申请日:2006-03-03

    申请人: Kenji Noda

    发明人: Kenji Noda

    IPC分类号: G11C11/34

    摘要: A memory circuit includes a latch having a first node and a second node, a first MIS transistor having source/drain nodes thereof coupled to the first node and to a plate line, respectively, and a gate node thereof coupled to a word selecting line, a second MIS transistor having source/drain nodes thereof coupled to the second node and to the plate line, respectively, and a gate node thereof coupled to the word selecting line, and a driver circuit configured to set the plate line to a first potential causing the first node to serve as a source node of the first MIS transistor in a first operation mode and to a second potential causing the first node to serve as a drain node of the first MIS transistor in a second operation mode, the first operation mode causing a lingering change in characteristics of the first MIS transistor.

    摘要翻译: 存储电路包括具有第一节点和第二节点的锁存器,第一MIS晶体管分别具有耦合到第一节点和板线的源极/漏极节点,以及耦合到字选择线的栅极节点, 第二MIS晶体管,其源极/漏极节点分别耦合到第二节点和板极线,并且其栅极节点分别耦合到字选择线,以及驱动器电路,其被配置为将板线设置为第一电位, 所述第一节点在第一操作模式中用作所述第一MIS晶体管的源节点,以及在第二操作模式中使所述第一节点用作所述第一MIS晶体管的漏极节点的第二电位,所述第一操作模式导致 第一MIS晶体管的特性的持续变化。

    Method for accessing abdominal cavity and medical procedure via natural orifice
    65.
    发明申请
    Method for accessing abdominal cavity and medical procedure via natural orifice 审中-公开
    通过自然孔进入腹腔和医疗程序的方法

    公开(公告)号:US20070163585A1

    公开(公告)日:2007-07-19

    申请号:US11331974

    申请日:2006-01-13

    IPC分类号: A61M16/00

    摘要: The method for accessing the abdominal cavity according to the present invention, includes: introducing a first flow path into the abdominal cavity; introducing a second flow path into the hollow organ from the natural orifice of the living body, and performing a pressure control, using the first flow path and the second flow path, so that the pressure within the hollow organ is lower than the pressure of the abdominal cavity, and forming an opening in the wall of the hollow organ from the inside of the hollow organ when the pressure within the abdominal cavity, as accomplished by pressure control, is equal to or lower than the pressure of the abdominal cavity, and inserting a device for performing a medical procedure through the opening.

    摘要翻译: 根据本发明的用于进入腹腔的方法包括:将第一流路引入腹腔; 从生物体的天然孔引入第二流路进入中空器官,并使用第一流路和第二流路进行压力控制,使得中空器官内的压力低于中空器官的压力 并且当通过压力控制实现的腹腔内的压力等于或低于腹腔的压力时,从中空器官的内部在中空器官的壁中形成开口,并且插入 用于通过开口执行医疗程序的装置。

    Method of fabricating semiconductor device
    67.
    发明授权
    Method of fabricating semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号:US06417038B1

    公开(公告)日:2002-07-09

    申请号:US09239678

    申请日:1999-01-29

    申请人: Kenji Noda

    发明人: Kenji Noda

    IPC分类号: H01L218238

    CPC分类号: H01L21/823807

    摘要: There is provided a method of fabricating a semiconductor device, including the steps of (a) forming both a p-well region and an n-well region at a surface of a semiconductor substrate, and (b) forming an n-type epitaxial layer on both the p- and n-well regions so that the n-type epitaxial layer contains impurities therein at a concentration lower than a concentration of impurities contained in the n-well region. For instance, the n-type epitaxial layer is formed by chemical vapor deposition in which a process gas including phosphorus or arsenic compounds therein is used. In accordance with the method, it is possible to optimize threshold voltages of both n-type and p-type transistors in a low-impurity channel transistor at a smaller number of steps. This ensures reduction in fabrication cost and enhancement in a fabrication yield.

    摘要翻译: 提供一种制造半导体器件的方法,包括以下步骤:(a)在半导体衬底的表面形成p阱区和n阱区,以及(b)形成n型外延层 在p阱区和n阱区两者上,使得n型外延层的浓度低于n阱区所含的杂质浓度。 例如,通过使用其中包含磷或砷化合物的工艺气体的化学气相沉积形成n型外延层。 根据该方法,可以以较少数量的步骤来优化低杂质通道晶体管中的n型和p型晶体管的阈值电压。 这确保了制造成本的降低和制造成品率的提高。

    Semiconductor memory device and method of manufacturing the same
    68.
    发明授权
    Semiconductor memory device and method of manufacturing the same 失效
    半导体存储器件及其制造方法

    公开(公告)号:US06175138B1

    公开(公告)日:2001-01-16

    申请号:US09294090

    申请日:1999-04-19

    申请人: Kenji Noda

    发明人: Kenji Noda

    IPC分类号: H01L2976

    CPC分类号: H01L27/11 Y10S257/903

    摘要: In a memory device of an SRAM, a threshold voltage (Vthn) of each driving MOS transistor consisting of the N-type MOS transistor is set larger than a threshold voltage (Vthp) of each MOS transistor for selecting an address consisting of the P-type MOS transistor.

    摘要翻译: 在SRAM的存储器件中,将由N型MOS晶体管组成的每个驱动MOS晶体管的阈值电压(Vthn)设定为大于用于选择由P-型MOS晶体管构成的地址的MOS晶体管的阈值电压(Vthp) 型MOS晶体管。

    Low-power consumption simple row addressing system incorporated in
semiconductor memory device for boosting selected word line over power
voltage level
    69.
    发明授权
    Low-power consumption simple row addressing system incorporated in semiconductor memory device for boosting selected word line over power voltage level 失效
    并入半导体存储器件中的低功耗简单行寻址系统,用于通过电源电压电平升高所选择的字线

    公开(公告)号:US5373479A

    公开(公告)日:1994-12-13

    申请号:US067091

    申请日:1993-05-26

    申请人: Kenji Noda

    发明人: Kenji Noda

    CPC分类号: G11C8/10 G11C8/08

    摘要: A row addressing system is responsive to row address bits for selecting one of row addresses respectively assigned to word lines, and comprises a row address buffer unit for producing row address predecoded signals from said row address bits, a word line driving unit responsive to a row address decoded signal for selectively driving the word lines and a row address decoder unit including a plurality of row address decoder circuits coupled between the row address buffer unit and the word line driving unit, wherein each row address decoder circuit has a flip flop circuit coupled between a boosted voltage line and a pair of output nodes for maintaining voltage levels at the pair of output nodes, a reset circuit coupled between one of the output nodes and a ground voltage line and responsive to a precharging signal of a power voltage level for charging the other output node to the boosted voltage level, and a decoder coupled between the other output node and the ground voltage line and responsive to the row address predecoded signals for producing the row address decoded signal so that the precharging signal of the power voltage level decreases current consumption without sacrifice of simple circuit arrangement.

    摘要翻译: 行寻址系统响应于用于选择分配给字线的行地址之一的行地址位,并且包括用于从所述行地址位产生行地址预解码信号的行地址缓冲单元,响应于行的字线驱动单元 用于选择性地驱动字线的地址解码信号和包括耦合在行地址缓冲器单元和字线驱动单元之间的多个行地址解码器电路的行地址解码器单元,其中每行行地址解码器电路具有耦合在 升压电压线和一对输出节点,用于维持所述一对输出节点处的电压电平;耦合在所述输出节点之一和接地电压线之间的复位电路,并响应用于对所述输出节点充电的电源电压电平的预充电信号 其他输出节点到升压电压电平,以及耦合在另一个输出节点和地电压线之间的解码器 代表行地址预编码信号,用于产生行地址解码信号,使得电源电压电平的预充电信号降低电流消耗,而不牺牲简单的电路布置。