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公开(公告)号：US20210176417A1
公开(公告)日：2021-06-10
申请号：US16708135
申请日：2019-12-09
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Chengcheng Xu , Rui Wang , Bi Yuan , Liang Zuo
IPC: H04N5/378 , H04N5/3745
Abstract: An image sensing device includes an image sensing circuit, a voltage supply grid, bitlines, and a control circuit. The image sensing circuit includes pixels arranged in rows and columns. Each one of the bitlines is coupled to a corresponding one of the columns. The voltage supply grid is coupled to the pixels. The control circuit is coupled to output at least a row select signal and a transfer signal to the rows. Each one of the rows is selectively coupled to the bitlines to selectively output image data signals in response to the row select signal and the transfer signal. Each one of the rows is further selectively coupled to the bitlines to selectively clamp the bitlines in response to the row select signal and the transfer signal. Each one of the rows is selectively decoupled from the bitlines in response to the row select signal.
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公开(公告)号：US10834351B2
公开(公告)日：2020-11-10
申请号：US16199887
申请日：2018-11-26
Applicant: OmniVision Technologies, Inc.
Inventor： Rui Wang , Tiejun Dai , Ling Fu , Jiayu Guo
Abstract: An image sensor includes pixel circuitry with a photodiode to receive light and output a pixel signal. The image sensor also includes readout circuitry with a first sample and hold transistor coupled to the pixel circuitry, and a first capacitor coupled to the first sample and hold transistor to receive the pixel signal. A second sample and hold transistor is coupled to the pixel circuitry, and a second capacitor is coupled to the second sample and hold transistor to receive the pixel signal. A first output switch is coupled to output the pixel signal from the first capacitor, and a second output switch is coupled to output the pixel signal from the second capacitor. A boost transistor is coupled to connect the first output switch and the second output switch when the boost transistor is turned on.
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公开(公告)号：US20200295739A1
公开(公告)日：2020-09-17
申请号：US16352673
申请日：2019-03-13
Applicant: OmniVision Technologies, Inc.
Inventor： Liang Zuo , Rui Wang , Hiroaki Ebihara , Nijun Jiang
Abstract: A ramp generator includes an integrator including a first stage having first and second inputs and first and second outputs, and a second stage including first and second transistors coupled between a power supply rail and ground. A node between the first and second transistors is coupled to the output of the integrator amplifier. A control terminal of the first transistor is coupled to the first output of the first stage, and a control terminal of the second transistor is coupled to the second output of the first stage. A first current flows from the output to ground during a ramp event in the ramp signal generated from the output. Trimming circuitry is coupled to the output of the integrator amplifier to provide a second current to the output of the integrator amplifier in response to trimming inputs. The second current substantially matches the first current.
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公开(公告)号：US20200169682A1
公开(公告)日：2020-05-28
申请号：US16199887
申请日：2018-11-26
Applicant: OmniVision Technologies, Inc.
Inventor： Rui Wang , Tiejun Dai , Ling Fu , Jiayu Guo
Abstract: An image sensor includes pixel circuitry with a photodiode to receive light and output a pixel signal. The image sensor also includes readout circuitry with a first sample and hold transistor coupled to the pixel circuitry, and a first capacitor coupled to the first sample and hold transistor to receive the pixel signal. A second sample and hold transistor is coupled to the pixel circuitry, and a second capacitor is coupled to the second sample and hold transistor to receive the pixel signal. A first output switch is coupled to output the pixel signal from the first capacitor, and a second output switch is coupled to output the pixel signal from the second capacitor. A boost transistor is coupled to connect the first output switch and the second output switch when the boost transistor is turned on.
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公开(公告)号：US10263031B2
公开(公告)日：2019-04-16
申请号：US15421911
申请日：2017-02-01
Applicant: OmniVision Technologies, Inc.
Inventor： Rui Wang , Hiroaki Ebihara , Zheng Yang , Chun-Ming Tang , Chao-Fang Tsai , Tiejun Dai
IPC: H01J40/14 , H01L27/146 , H04N5/3745 , H04N5/369
Abstract: A hybrid-bonded image sensor has a photodiode die with multiple macrocells; each macrocell has at least one photodiode and a coupling region. The coupling regions couple to a coupling region of a macrocell unit of a supporting circuitry die where they feed an input of an amplifier and a feedback capacitor. The feedback capacitor also couples to output of the amplifier, and the amplifier inverts between the input and the output. The method includes resetting a photodiode of the photodiode die; coupling signal from photodiode through the bond point to the supporting circuitry die to a feedback capacitor and to an input of the amplifier, the feedback capacitor also coupled to an inverting output of the amplifier; and amplifying the signal with the amplifier, where a capacitance of the feedback capacitor determines a gain of the amplifier.
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Patent Agency Ranking
公开(公告)号：US09344658B2
公开(公告)日：2016-05-17
申请号：US14448154
申请日：2014-07-31
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Tiejun Dai , Rui Wang , Dyson H. Tai , Sohei Manabe
IPC: H01L27/00 , H04N5/378 , H04N5/376 , H01L27/146
CPC classification number: H04N5/378 , H01L27/14612 , H01L27/14634 , H01L27/14636 , H04N5/376
Abstract: A pixel cell includes a photodiode disposed within a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode. A transfer transistor is disposed within the first semiconductor chip and coupled to the photodiode to transfer the image charge from the photodiode. A bias voltage generation circuit disposed within a second semiconductor chip for generating a bias voltage. The bias voltage generation circuit is coupled to the first semiconductor chip to bias the photodiode with the bias voltage. The bias voltage is negative with respect to a ground voltage of the second semiconductor chip. A floating diffusion is disposed within the second semiconductor chip. The transfer transistor is coupled to transfer the image charge from the photodiode on the first semiconductor chip to the floating diffusion on the second semiconductor chip.
Abstract translation: 像素单元包括设置在第一半导体芯片内的光电二极管，用于响应入射在光电二极管上的光累积图像电荷。 传输晶体管设置在第一半导体芯片内并耦合到光电二极管以从光电二极管传输图像电荷。 偏置电压产生电路，设置在第二半导体芯片内，用于产生偏置电压。 偏置电压产生电路耦合到第一半导体芯片以偏置偏压的光电二极管。 偏置电压相对于第二半导体芯片的接地电压为负。 浮置扩散部设置在第二半导体芯片内。 传输晶体管被耦合以将图像电荷从第一半导体芯片上的光电二极管转移到第二半导体芯片上的浮动扩散。
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公开(公告)号：US20160054447A1
公开(公告)日：2016-02-25
申请号：US14464453
申请日：2014-08-20
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Tianjia Sun , Rui Wang , Tiejun Dai
CPC classification number: G01S17/89 , G01S7/4863 , G01S17/10
Abstract: A programmable current source for use with a time of flight pixel cell includes a first transistor. A current through the first transistor is responsive to a gate-source voltage of the first transistor. A current control circuit is coupled to the first transistor and coupled to a reference current source to selectively couple a reference current of the reference current source through the first transistor during a sample operation. A sample and hold circuit is coupled to the first transistor to sample a gate-source voltage of the first transistor during the sample operation. The sample and hold circuit is coupled to hold the gate-source voltage during a hold operation after the sample operation substantially equal to the gate-source voltage during the sample operation. A hold current through the first transistor during the hold operation is substantially equal to the reference current.
Abstract translation: 与飞行时间像素单元一起使用的可编程电流源包括第一晶体管。 通过第一晶体管的电流响应于第一晶体管的栅极 - 源极电压。 电流控制电路耦合到第一晶体管并耦合到参考电流源，以在采样操作期间选择性地将参考电流源的参考电流耦合通过第一晶体管。 采样和保持电路耦合到第一晶体管以在采样操作期间对第一晶体管的栅源电压进行采样。 在采样操作期间，在采样操作期间基本上等于栅极 - 源极电压的保持操作期间，采样和保持电路被耦合以保持栅极 - 源极电压。 在保持操作期间通过第一晶体管的保持电流基本上等于参考电流。
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68.发明申请LOW POWER IMAGING SYSTEM WITH SINGLE PHOTON AVALANCHE DIODE PHOTON COUNTERS AND GHOST IMAGE REDUCTION 有权具有单光子光电二极管光子计数器和减少图像的低功率成像系统公开(公告)号：US20150163429A1
公开(公告)日：2015-06-11
申请号：US14100941
申请日：2013-12-09
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Tiejun Dai , Rui Wang
CPC classification number: H04N5/378 , H04N5/3535 , H04N5/35545 , H04N5/35554 , H04N5/35572 , H04N5/37455
Abstract: An imaging system includes a pixel array including a plurality of pixels. Each one of the pixels includes a single photon avalanche diode (SPAD) coupled to detect photons in response to incident light. A photon counter included in readout circuitry coupled to each pixel to count a number of photons detected by each pixel. The photon counter is coupled to stop counting photons in each pixel when a threshold photon count is reached for each pixel. Control circuitry is coupled to the pixel array to control operation of the pixel array. The control circuitry includes an exposure time counter coupled to count a number of exposure times elapsed before each pixel detects the threshold photon count. Respective exposure time counts and photon counts are combined for each pixel of the pixel array.
Abstract translation: 成像系统包括包括多个像素的像素阵列。 每个像素包括耦合以响应于入射光检测光子的单个光子雪崩二极管（SPAD）。 包括在耦合到每个像素的读出电路中的光子计数器以对由每个像素检测的多个光子进行计数。 当达到每个像素的阈值光子计数时，光子计数器被耦合以停止计数每个像素中的光子。 控制电路耦合到像素阵列以控制像素阵列的操作。 控制电路包括曝光时间计数器，其被耦合以对每个像素检测到阈值光子计数之前经过的曝光次数进行计数。 对像素阵列的每个像素组合相应的曝光时间计数和光子计数。
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公开(公告)号：US20250030962A1
公开(公告)日：2025-01-23
申请号：US18353680
申请日：2023-07-17
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Rui Wang , Takayuki Goto
Abstract: A pixel array includes a plurality of pixel cells, each including a photodiode configured to photogenerate image charge in response to the incident light, a first floating diffusion (FD) coupled to receive the image charge from the photodiode, a reset transistor coupled between a voltage source and the first FD, a second FD coupled between the first FD and ground, a first dual FD transistor coupled between the first and second FDs. Second FDs of first and second pixel cells are coupled. Second FDs of third and fourth pixel cells are coupled.
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公开(公告)号：US20240284074A1
公开(公告)日：2024-08-22
申请号：US18171227
申请日：2023-02-17
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Rui Wang , Hiroaki Ebihara
Abstract: A pixel cell readout circuit comprises a comparator with a current mirror having first and second current paths, a first input transistor coupled to the first current path, a low conversion gain (LCG) second input transistor selectively coupled to the second current path, and a high conversion gain (HCG) second input transistor selectively coupled to the second current path. The pixel cell readout circuit further comprises a gain network coupled between a gate node of the first input transistor and a ramp generator output, wherein the gain network is configured to provide a variable comparator gain to the comparator, an LCG auto-zero switch coupled between a drain node and a gate node of the LCG second input transistor, and an HCG auto-zero switch coupled between a drain node and a gate node of the HCG second input transistor.
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