公开(公告)号：US06169324A

公开(公告)日：2001-01-02

申请号：US09413754

申请日：1999-10-06

申请人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

发明人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

IPC分类号： H01L2144

CPC分类号： H01L27/10852 ,  G03F7/70333 ,  G03F9/70 ,  H01L21/28512 ,  H01L21/76 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823807 ,  H01L23/291 ,  H01L23/4951 ,  H01L23/5258 ,  H01L23/532 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0922 ,  H01L27/0928 ,  H01L27/10808 ,  H01L28/40 ,  H01L2223/54473 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  Y10S257/90 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

摘要翻译： 这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，其包括：形成步骤 通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤， 面具已被删除。

公开(公告)号：US5930624A

公开(公告)日：1999-07-27

申请号：US13605

申请日：1998-01-26

申请人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

发明人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/105 ,  H01L27/10808

摘要： A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. In a first aspect, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In other aspects, a Y-select signal line overlaps the lower electrode layer of the capacitor element; a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region; the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it, the capacitor dielectric film being a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure; an aluminum wiring layer and a protective (and/or barrier) layer are formed by sputtering in the same vacuum sputtering chamber without breaking the vacuum between forming the layers; and a refractory metal, or a refractory metal silicide, is used as the protective layer for an aluminum wiring containing an added element (e.g., Cu) to prevent migration.

摘要翻译： 公开了一种具有开关MISFET的半导体集成电路器件和形成在半导体衬底上的电容器元件。 在第一方面中，电容器元件连接的开关MISFET的半导体区域的杂质浓度小于外围电路的MISFET的半导体区域的杂质浓度。 在其他方面，Y选择信号线与电容器元件的下电极层重叠; 至少在与电容器元件连接的开关MISFET的半导体区域下方设置的势垒层通过用于沟道阻挡区域的杂质的扩散而形成; 电容器元件的电介质膜与其上的电容器电极层共同扩展，电容器电介质膜是其上具有氧化硅层的氮化硅膜，氧化硅层通过氧化氮化硅的表面层而形成 在高压下 通过溅射在相同的真空溅射室中形成铝布线层和保护（和/或阻挡层），而不破坏形成层之间的真空; 和难熔金属或难熔金属硅化物用作用于包含添加元素（例如Cu）以防止迁移的铝布线的保护层。

公开(公告)号：US5780882A

公开(公告)日：1998-07-14

申请号：US456788

申请日：1995-06-01

申请人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

发明人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

IPC分类号： G03F7/20 ,  G03F9/00 ,  H01L21/02 ,  H01L21/285 ,  H01L21/336 ,  H01L21/76 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/29 ,  H01L23/495 ,  H01L23/525 ,  H01L23/532 ,  H01L23/544 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L27/02

CPC分类号： H01L27/10852 ,  G03F7/70333 ,  G03F9/70 ,  H01L21/28512 ,  H01L21/76 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823807 ,  H01L23/291 ,  H01L23/4951 ,  H01L23/5258 ,  H01L23/532 ,  H01L23/544 ,  H01L27/0922 ,  H01L28/40 ,  H01L2223/54473 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0928 ,  H01L27/10808 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  Y10S257/90

摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

公开(公告)号：US20090225008A1

公开(公告)日：2009-09-10

申请号：US12323592

申请日：2008-11-26

申请人： Shunichiro Nobuki ,  Norihiro Uemura ,  Masakazu Sagawa ,  Keizo Suzuki ,  Yoshiro Mikami ,  Hideto Momose ,  Shirun Ho

发明人： Shunichiro Nobuki ,  Norihiro Uemura ,  Masakazu Sagawa ,  Keizo Suzuki ,  Yoshiro Mikami ,  Hideto Momose ,  Shirun Ho

IPC分类号： G09G3/28

CPC分类号： H01J11/26 ,  H01J11/12 ,  H01J11/24 ,  H01J11/36 ,  H01J2211/245 ,  H01J2211/265 ,  H01J2211/365

摘要： A plasma display apparatus having a priming discharge region PDC partitioned from a display discharge cell DDC, by a traverse rib, at a side where the second electrode between the display discharge cell DDC adjacent in a row direction is adjacent; a second longitudinal rib partitioning the priming discharge region PDC; a third longitudinal rib, further partitioning a region partitioned by the second longitudinal rib into two sections; a convex electrode; and a gap connecting the display discharge cell DDC and the priming discharge cell PDC, wherein a sum of a width in a line direction of a nearly rectangular space region containing adjacent two priming discharge cells PDCs, and a pattern width of the second longitudinal rib is designed larger than a sum of a width in the row direction and a pattern width of the traverse rib.

摘要翻译： 一种等离子体显示装置，在显示用放电单元DDC与行方向相邻的显示用放电单元DDC之间的第二电极相邻的一侧，通过横动肋从显示用放电单元DDC分割的起动放电区域PDC; 分隔起动放电区域PDC的第二纵向肋; 第三纵向肋，进一步将由所述第二纵向肋分隔的区域划分成两个部分; 凸电极 以及连接显示放电单元DDC和起动放电单元PDC的间隙，其中，包含相邻两个起动放电单元PDC的近似矩形的空间区域的线方向的宽度与第二纵向肋的图案宽度之和为 设计成大于行方向宽度和横幅的图案宽度之和。

公开(公告)号：US20090184895A1

公开(公告)日：2009-07-23

申请号：US12344672

申请日：2008-12-29

申请人： Norihiro Uemura ,  Shunichiro Nobuki ,  Masakazu Sagawa ,  Shirun Ho ,  Keizo Suzuki ,  Yoshiro Mikami

发明人： Norihiro Uemura ,  Shunichiro Nobuki ,  Masakazu Sagawa ,  Shirun Ho ,  Keizo Suzuki ,  Yoshiro Mikami

IPC分类号： G09G3/28

CPC分类号： H01J11/24 ,  H01J11/12 ,  H01J11/32 ,  H01J11/36

摘要： A high-definition, high-quality, and high-contrast PDP that features high brightness, guaranteed long life, and stable driving, is provided by improving the time-dependent degradation of address discharge delay. The PDP includes: a front substrate having bus electrodes, and sustain discharge electrodes extending in a lateral direction of the bus electrodes to form display lines; a back substrate having address electrodes facing the sustain discharge electrodes in the lateral direction of the bus electrodes; and discharge cells formed between the substrates. Each of the discharge cells includes a sustain discharge cell and a priming discharge cell, in which a protruding electrode is formed to extend in a direction opposite to the discharge gap from the bus electrode, and a predetermined space is provided between the two cells to supply priming. The shape and size of the space are optimized so that the sustain discharge does not spread to the address discharge cell through the space.

摘要翻译： 通过改善寻址放电延迟的时间依赖性降低，提供了具有高亮度，长寿命和稳定驱动的高清晰度，高质量和高对比度的PDP。 PDP包括：具有总线电极的前基板和沿总线电极的横向方向延伸的维持放电电极，以形成显示线; 背面基板，其具有在所述总线电极的横向方向上面对所述维持放电电极的寻址电极; 以及在基板之间形成的放电单元。 每个放电单元包括维持放电单元和起动放电单元，其中突出电极形成为沿着与总线电极的放电间隙相反的方向延伸，并且在两个单元之间提供预定的空间以供应 起动 优化空间的形状和尺寸，使得维持放电不会通过该空间扩散到寻址放电单元。

公开(公告)号：US20080129187A1

公开(公告)日：2008-06-05

申请号：US11943690

申请日：2007-11-21

申请人： Takuo Tamura ,  Masakazu Sagawa ,  Hiroshi Kikuchi

发明人： Takuo Tamura ,  Masakazu Sagawa ,  Hiroshi Kikuchi

IPC分类号： H01J1/62

CPC分类号： H01J31/127 ,  H01J29/04 ,  H01J2329/0484

摘要： An image display device in which each pixel has a thin-film electron source composed of a lower electrode (which is a signal wire), an electron accelerating layer (which is formed by anodizing the surface of said signal wire), and an upper electrode (which covers said electron accelerating layer and releases electrons), in which the anodized film constituting said electron accelerating layer contains hydrated alumina component and anhydrous alumina component such that their ratio in the side close to the upper electrode is greater than that in the side close to the lower electrode. This structure prevents said thin-film electron source from being deteriorated in diode characteristics by said electron accelerating layer, thereby enhancing the reliability of said image display device.

摘要翻译： 一种图像显示装置，其中每个像素具有由下电极（其是信号线），电子加速层（通过阳极氧化所述信号线的表面形成）构成的薄膜电子源，以及上电极 （其覆盖所述电子加速层并释放电子），其中构成所述电子加速层的阳极氧化膜含有水合氧化铝组分和无水氧化铝组分，使得它们在靠近上电极的一侧的比例大于侧面密封 到下电极。 该结构防止所述电子加速层使所述薄膜电子源的二极管特性劣化，从而提高所述图像显示装置的可靠性。

公开(公告)号：US06342412B1

公开(公告)日：2002-01-29

申请号：US09459921

申请日：1999-12-14

申请人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

发明人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

IPC分类号： H01L21336

CPC分类号： H01L27/10852 ,  G03F7/70333 ,  G03F9/70 ,  H01L21/28512 ,  H01L21/76 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823807 ,  H01L23/291 ,  H01L23/4951 ,  H01L23/5258 ,  H01L23/532 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0922 ,  H01L27/0928 ,  H01L27/10808 ,  H01L28/40 ,  H01L2223/54473 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  Y10S257/90 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

公开(公告)号：US06281071B1

公开(公告)日：2001-08-28

申请号：US09317999

申请日：1999-05-25

申请人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

发明人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

IPC分类号： H01L218242

CPC分类号： H01L27/105 ,  H01L27/10808

摘要： A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, such as a DRAM, is disclosed. In a first aspect of the present invention, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In a second aspect, the Y-select signal line overlaps the lower electrode layer of the capacitor element. In a third aspect, a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. In a fourth aspect, the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it. In a fifth aspect, the capacitor dielectric film is a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure. In sixth and seventh aspects, wiring is provided.

摘要翻译： 公开了一种具有开关MISFET的半导体集成电路器件和形成在诸如DRAM的半导体衬底之上的电容器元件。 在本发明的第一方面中，电容器元件连接的开关MISFET的半导体区域的杂质浓度小于外围电路的MISFET的半导体区域的杂质浓度。 在第二方面，Y选择信号线与电容器元件的下电极层重叠。 在第三方面中，通过用于沟道阻挡区域的杂质的扩散，形成至少在电容器元件连接的开关MISFET的半导体区域下方的势垒层。 在第四方面中，电容器元件的电介质膜与其上的电容器电极层共同扩展。 在第五方面中，电容器电介质膜是其上具有氧化硅层的氮化硅膜，通过在高压下氧化氮化硅的表面层而形成氧化硅层。 在第六和第七方面中，提供了布线。

公开(公告)号：US5753550A

公开(公告)日：1998-05-19

申请号：US620867

申请日：1996-03-25

申请人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

发明人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/105 ,  H01L27/10808

摘要： A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. In a first aspect, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In other aspects, a Y-select signal line overlaps the lower electrode layer of the capacitor element; a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region; the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it, the capacitor dielectric film being a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure; an aluminum wiring layer and a protective (and/or barrier) layer are formed by sputtering in the same vacuum sputtering chamber without breaking the vacuum between forming the layers; and a refractory metal, or a refractory metal silicide, is used as the protective layer for an aluminum wiring containing an added element (e.g., Cu) to prevent migration.

摘要翻译： 公开了一种具有开关MISFET的半导体集成电路器件和形成在半导体衬底上的电容器元件。 在第一方面中，电容器元件所连接的开关MISFET的半导体区域的杂质浓度小于外围电路的MISFET的半导体区域的杂质浓度。 在其他方面，Y选择信号线与电容器元件的下电极层重叠; 至少在与电容器元件连接的开关MISFET的半导体区域下方设置的势垒层通过用于沟道阻挡区域的杂质的扩散而形成; 电容器元件的电介质膜与其上的电容器电极层共同扩展，电容器电介质膜是其上具有氧化硅层的氮化硅膜，氧化硅层通过氧化氮化硅的表面层而形成 在高压下 通过溅射在相同的真空溅射室中形成铝布线层和保护（和/或阻挡层），而不破坏形成层之间的真空; 和难熔金属或难熔金属硅化物用作用于包含添加元素（例如Cu）以防止迁移的铝布线的保护层。

公开(公告)号：US5557147A

公开(公告)日：1996-09-17

申请号：US230021

申请日：1994-04-19

申请人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

发明人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

IPC分类号： G03F7/20 ,  G03F9/00 ,  H01L21/02 ,  H01L21/285 ,  H01L21/336 ,  H01L21/76 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/29 ,  H01L23/495 ,  H01L23/525 ,  H01L23/532 ,  H01L23/544 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L29/68 ,  H01L29/06 ,  H01L29/34

CPC分类号： H01L27/10852 ,  G03F7/70333 ,  G03F9/70 ,  H01L21/28512 ,  H01L21/76 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823807 ,  H01L23/291 ,  H01L23/4951 ,  H01L23/5258 ,  H01L23/532 ,  H01L23/544 ,  H01L27/0922 ,  H01L28/40 ,  H01L2223/54473 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0928 ,  H01L27/10808 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  Y10S257/90

摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.