公开(公告)号：US5336427A

公开(公告)日：1994-08-09

申请号：US4262

申请日：1993-01-14

申请人： Charles J. Bunczk ,  Peter A. Burke ,  William R. Camp ,  John L. Orehotsky

发明人： Charles J. Bunczk ,  Peter A. Burke ,  William R. Camp ,  John L. Orehotsky

IPC分类号： C11D1/22 ,  C11D1/24 ,  C11D3/18 ,  C11D3/37 ,  C11D3/395 ,  C11D17/00 ,  C11D3/20 ,  C11D3/43

CPC分类号： C11D3/3738 ,  C11D17/0056 ,  C11D3/18 ,  C11D3/373 ,  C11D3/3749 ,  C11D3/3955 ,  C11D1/22 ,  C11D1/24

摘要： In a solid lavatory cleansing block or tablet containing a surfactant, a germicide agent or an oxidizing agent and fillers, the improvement which comprises said cleansing block having a stabilizer selected from the group consisting of mineral oil, silicone fluids and polybutene in an amount from about 0.1 to 8% by weight of the composition.

摘要翻译： 在含有表面活性剂，杀菌剂或氧化剂和填料的固体洗手间清洁块或片剂中，其改进包括所述清洁块具有选自矿物油，硅氧烷流体和聚丁烯的稳定剂，其量为约 0.1至8重量％的组合物。

公开(公告)号：US4722801A

公开(公告)日：1988-02-02

申请号：US876923

申请日：1986-06-20

申请人： Charles J. Bunczk ,  Peter A. Burke ,  Edward Strauch

发明人： Charles J. Bunczk ,  Peter A. Burke ,  Edward Strauch

IPC分类号： A61L9/05 ,  C11D1/72 ,  C11D1/74 ,  C11D1/825 ,  C11D3/02 ,  C11D3/04 ,  C11D3/22 ,  C11D3/37 ,  C11D17/00 ,  C11D3/20

CPC分类号： C11D3/046 ,  A61L9/05 ,  C11D1/74 ,  C11D1/825 ,  C11D17/0056 ,  C11D3/222 ,  C11D3/3707 ,  C11D1/72

摘要： Solid cake lavoratory cleansing block compositions comprising polyethylene glycol distearate having a dissolution time of at least 5.5 hours, and optional ingredients which include a gelling natural gum, fragrances, dyes, solid binders, filler material and mixtures thereof.

公开(公告)号：US08629488B2

公开(公告)日：2014-01-14

申请号：US12108361

申请日：2008-04-23

申请人： Sallie Hose ,  Derryl Allman ,  Peter A. Burke ,  Ponce Saopraseuth

发明人： Sallie Hose ,  Derryl Allman ,  Peter A. Burke ,  Ponce Saopraseuth

IPC分类号： G11C11/00

CPC分类号： H01L28/75

摘要： An energy storage device such as a metal-insulator-metal capacitor and a method for manufacturing the energy storage device. The metal-insulator-metal capacitor includes an insulating material positioned between a bottom electrode or bottom plate and a top electrode or top plate. The surface area of the bottom electrode is greater than the surface area of the insulating material and the surface area of the insulating material is greater than the surface area of the top electrode. The top electrode and the insulating layer have edges that are laterally within and spaced apart from edges of the bottom electrode. A protective layer covers the top electrode, the edges of the top electrode, and the portions of the insulating layer that are uncovered by the top electrode. The protective layer serves as an etch mask during the formation of the bottom electrode.

摘要翻译： 诸如金属 - 绝缘体 - 金属电容器的能量存储装置和用于制造储能装置的方法。 金属 - 绝缘体 - 金属电容器包括位于底部电极或底板与顶部电极或顶板之间的绝缘材料。 底部电极的表面积大于绝缘材料的表面积，并且绝缘材料的表面积大于顶部电极的表面积。 顶部电极和绝缘层具有横向在底部电极的边缘内并与其间隔开的边缘。 保护层覆盖顶部电极，顶部电极的边缘和绝缘层的未被顶部电极覆盖的部分。 在形成底部电极期间，保护层用作蚀刻掩模。

公开(公告)号：US20130323921A1

公开(公告)日：2013-12-05

申请号：US13482920

申请日：2012-05-29

申请人： Peter A. Burke ,  Eric J. Ameele

发明人： Peter A. Burke ,  Eric J. Ameele

IPC分类号： H01L21/283 ,  H01L21/31

CPC分类号： H01L29/7813 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L29/401 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397

摘要： In one embodiment, a trench shield electrode layer is separated from a trench gate electrode by an inter-electrode dielectric layer. A conformal deposited dielectric layer is formed as part of a gate dielectric structure and further isolates the trench shield electrode from the trench gate electrode. The conformal deposited dielectric layer is formed using an improved high temperature oxide (HTO) low pressure chemical vapor deposition (LPCVD) process.

摘要翻译： 在一个实施例中，沟槽屏蔽电极层通过电极间介电层与沟槽栅电极分离。 形成共形沉积介电层作为栅极电介质结构的一部分，并进一步将沟槽屏蔽电极与沟槽栅电极隔离。 使用改进的高温氧化物（HTO）低压化学气相沉积（LPCVD）工艺形成共形沉积介电层。

公开(公告)号：US07928521B1

公开(公告)日：2011-04-19

申请号：US11142725

申请日：2005-05-31

申请人： Peter A. Burke ,  Thomas Rueckes ,  Claude L. Bertin

发明人： Peter A. Burke ,  Thomas Rueckes ,  Claude L. Bertin

IPC分类号： H01L29/82

CPC分类号： H01H1/0094 ,  B82Y10/00 ,  H01H59/0009 ,  H01H2001/0042 ,  H01H2059/0045 ,  H01L51/0048 ,  H01L51/0591 ,  Y10S977/932

摘要： The invention comprises a carbon nanotube switch suitable for use in an integrated circuit structure and capable of being moved from a first position in a first plane in the switch to a second position in a second plane in the switch using approximately the same energy as required to move the switch from the second position back to the first position. The switch comprises a flexible carbon nanotube strip secured clamped at one end in a first plane in a switching chamber, and secured or clamped, at the opposite end of the carbon nanotube, in a second plane in the switching chamber, which is parallel to the first plane but spaced therefrom, to permit the central portion of the carbon nanotube strip to move in the chamber between a first position in the first plane and in electrical contact with one or more first electrodes and a second position in the second plane and in electrical contact with one or more second electrodes.

摘要翻译： 本发明包括一种适用于集成电路结构的碳纳米管开关，其能够使用开关中的第一平面中的第一位置移动到开关中的第二平面中的第二位置，使用大约相同的能量 将开关从第二个位置移回到第一个位置。 开关包括柔性碳纳米管条，其固定在切换室中的第一平面中的一端处夹持，并且在碳纳米管的相对端处固定或夹紧在开关室中的平行于第二平面的第二平面中 第一平面但与其间隔开，以允许碳纳米管条的中心部分在室中在第一平面中的第一位置和与一个或多个第一电极电连接并且在第二平面中的第二位置和电气 与一个或多个第二电极接触。

公开(公告)号：US07915122B2

公开(公告)日：2011-03-29

申请号：US11312849

申请日：2005-12-20

申请人： Richard J. Carter ,  Hemanshu D. Bhatt ,  Shiqun Gu ,  Peter A. Burke ,  James R. B. Elmer ,  Sey-Shing Sun ,  Byung-Sung Kwak ,  Verne Hornback

发明人： Richard J. Carter ,  Hemanshu D. Bhatt ,  Shiqun Gu ,  Peter A. Burke ,  James R. B. Elmer ,  Sey-Shing Sun ,  Byung-Sung Kwak ,  Verne Hornback

IPC分类号： H01L21/336

CPC分类号： H01L51/0018 ,  B82Y10/00 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0545 ,  Y10S977/742

摘要： A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.

摘要翻译： 一种形成自对准逻辑单元的方法。 在底部电极上形成纳米管层。 在纳米管层上形成夹层。 夹层覆盖纳米管层，从而保护纳米管层。 在钳位层上形成电介质层。 蚀刻介电层。 钳位层提供蚀刻停止并保护纳米管层。 用各向同性蚀刻剂蚀刻钳夹层，蚀刻介质层下方的夹层，产生电介质层的重叠，并引起钳位层和电介质层之间的自对准。 在纳米管层上形成间隔层。 除了围绕电介质层的边缘的环形部分之外，蚀刻间隔层。 除了夹持层，电介质层和间隔层中的至少一个的部分以外，蚀刻纳米管层，从而导致夹紧层之间的自对准，与电介质层的重叠，间隔层， 和纳米管层。

公开(公告)号：US20110027961A1

公开(公告)日：2011-02-03

申请号：US12902130

申请日：2010-10-11

申请人： Peter A. Burke ,  Sallie Hose ,  Sudhama C. Shastri

发明人： Peter A. Burke ,  Sallie Hose ,  Sudhama C. Shastri

IPC分类号： H01L21/02

CPC分类号： H01L23/5223 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76846 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/53238 ,  H01L28/20 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor component that includes an integrated passive device and method for manufacturing the semiconductor component. Vertically integrated passive devices are manufactured above a substrate. In accordance with one embodiment, a resistor is manufactured in a first level above a substrate, a capacitor is manufactured in a second level that is vertically above the first level, and a copper inductor is manufactured in a third level that is vertically above the second level. The capacitor has aluminum plates. In accordance with another embodiment, a resistor is manufactured in a first level above a substrate, a copper inductor is manufactured in a second level that is vertically above the first level, and a capacitor is manufactured in a third level that is vertically above the second level. The capacitor may have aluminum plates or a portion of the copper inductor may serve as one of its plates.

公开(公告)号：US07850925B2

公开(公告)日：2010-12-14

申请号：US11763574

申请日：2007-06-15

申请人： Michael A. Centanni ,  Peter A. Burke

发明人： Michael A. Centanni ,  Peter A. Burke

IPC分类号： A62B7/08 ,  A61L9/00

CPC分类号： A61L2/208 ,  A61L2/202 ,  A61L2/206 ,  A61L9/015 ,  A61L2202/13

摘要： A method and apparatus for aerating a region exposed to a gaseous/vaporous sterilant. A catalytic destroyer and a reactive chemical unit are used to reduce the concentration of the gaseous/vaporous sterilant within the region. The reactive chemical unit includes a chemistry that is chemically reactive with the gaseous/vaporous sterilant. In one embodiment, the gaseous/vaporous sterilant is vaporized hydrogen peroxide and the chemistry of the reactive chemical unit includes thiosulfate and iodide.

摘要翻译： 用于对暴露于气体/蒸气灭菌剂的区域进行曝气的方法和装置。 催化破坏剂和反应性化学单元用于降低该区域内气态/蒸气灭菌剂的浓度。 反应性化学单元包括与气态/蒸气灭菌剂化学反应的化学物质。 在一个实施方案中，气态/蒸气灭菌剂是蒸发的过氧化氢，并且反应性化学单元的化学性质包括硫代硫酸盐和碘化物。

公开(公告)号：US07646077B2

公开(公告)日：2010-01-12

申请号：US12191171

申请日：2008-08-13

申请人： Hong-Qiang Lu ,  Peter A. Burke ,  Wilbur G. Catabay

发明人： Hong-Qiang Lu ,  Peter A. Burke ,  Wilbur G. Catabay

IPC分类号： H01L23/58 ,  H01L21/4763

CPC分类号： H01L21/02211 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/02315 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/3121 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76832 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the insulating layer to expose a portion of the copper line. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer. A copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure. Aspects of the invention also include methods for forming the dielectric copper barrier layers and associate copper interconnects to the underlying copper lines.

摘要翻译： 本发明涉及改进的介电铜阻挡层和相关互连结构。 一种结构包括具有铜线的半导体衬底。 在下面的铜线上形成由硅和碳中的至少一种形成的绝缘层。 在绝缘层中形成开口以露出铜线的一部分。 绝缘层中的开口的内表面具有形成在其上的电介质阻挡层，以防止铜扩散到绝缘层中。 形成铜塞以填充开口并与下面的铜互连结构电接触。 本发明的方面还包括用于形成电介质铜阻挡层和将铜互连连接到下面的铜线的方法。

公开(公告)号：US20090256217A1

公开(公告)日：2009-10-15

申请号：US12102700

申请日：2008-04-14

申请人： Hongquiang Lu ,  Peter A. Burke ,  Wilbur Catabay

发明人： Hongquiang Lu ,  Peter A. Burke ,  Wilbur Catabay

IPC分类号： H01L27/00 ,  H01L21/02

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C23/00 ,  G11C2213/16 ,  H01L21/76849 ,  H01L23/485 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention is directed to structures and methods of fabricating nanotube electromechanical memory cells having a bottom electrode with a substantially planar contact surface. The bottom electrode is configured so that during the operation of the memory cell the nanotube crossbar of the cell can make contact with a substantially planar surface of the bottom electrode.

摘要翻译： 本发明涉及制造具有基本平坦的接触表面的底部电极的纳米管机电存储单元的结构和方法。 底部电极被配置为使得在存储器单元的操作期间，电池的纳米管横截面可以与底部电极的基本平坦的表面接触。