公开(公告)号：US20190035796A1

公开(公告)日：2019-01-31

申请号：US16150637

申请日：2018-10-03

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Ritu Chaba ,  Ping Liu ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC: H01L27/11 ,  G11C8/14 ,  G11C11/418 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L21/768 ,  H01L21/3213 ,  G11C11/419 ,  G11C8/16

Abstract: An apparatus includes first means for routing current coupled to a bit cell. The apparatus includes third means for routing current. The third means for routing current includes a write word line coupled to the bit cell. The apparatus includes second means for routing current. The second means for routing current is between the first means for routing current and the third means for routing current. The second means for routing current includes two read word lines coupled to the bit cell.

公开(公告)号：US10141317B2

公开(公告)日：2018-11-27

申请号：US15347530

申请日：2016-11-09

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Ritu Chaba ,  Ping Liu ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC: H01L27/11 ,  G11C8/14 ,  G11C11/418 ,  H01L27/02 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  G11C8/16 ,  G11C11/419

Abstract: An apparatus includes a first metal layer coupled to a bit cell. The apparatus also includes a third metal layer including a write word line that is coupled to the bit cell. The apparatus further includes a second metal layer between the first metal layer and the third metal layer. The second metal layer includes two read word lines coupled to the bit cell.

公开(公告)号：US10079293B2

公开(公告)日：2018-09-18

申请号：US15839050

申请日：2017-12-12

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Kern Rim ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  Vladimir Machkaoutsan ,  Da Yang ,  Choh Fei Yeap

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap.

公开(公告)号：US10043796B2

公开(公告)日：2018-08-07

申请号：US15097142

申请日：2016-04-12

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  John Jianhong Zhu ,  Junjing Bao ,  Jeffrey Junhao Xu ,  Da Yang ,  Matthew Michael Nowak ,  Choh Fei Yeap

IPC: H01L29/06 ,  H01L27/088 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/423 ,  H01L27/06

Abstract: A device includes a substrate, a first nanowire field effect transistor (FET), and a second nanowire FET positioned between the substrate and the first nanowire FET. The device also includes a first nanowire electrically coupled to the first nanowire FET and to the second nanowire FET.

公开(公告)号：US10037795B2

公开(公告)日：2018-07-31

申请号：US14499149

申请日：2014-09-27

Applicant: QUALCOMM Incorporated

Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: Systems and methods relate to a seven transistor static random-access memory (7T SRAM) bit cell which includes a first inverter having a first pull-up transistor, a first pull-down transistor, and a first storage node, and a second inverter having a second pull-up transistor, a second pull-down transistor, and a second storage node. The second storage node is coupled to gates of the first pull-up transistor and the first pull-down transistor. A transmission gate is configured to selectively couple the first storage node to gates of the second pull-up transistor and the second pull-down transistor during a write operation, a standby mode, and a hold mode, and selectively decouple the first storage node from gates of the first pull-up transistor and a first pull-down transistor during a read operation. The 7T SRAM bit cell can be read or written through an access transistor coupled to the first storage node.

公开(公告)号：US20170278842A1

公开(公告)日：2017-09-28

申请号：US15081702

申请日：2016-03-25

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Kern Rim ,  Choh Fei Yeap

IPC: H01L27/06 ,  H01L29/66 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66545 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/78696

Abstract: An integrated circuit includes a FinFET and a nanostructure FET. The integrated circuit includes a bulk substrate. The integrated circuit also includes a fin field effect transistor (FinFET) coupled to the bulk substrate. The FinFET includes a first source region, a first drain region, and a fin extending between the first source region and the first drain region. The integrated circuit also includes a nanostructure FET coupled to the bulk substrate. The nanostructure FET includes a second source region, a second drain region, and a stack of at least two nanostructures extending between the second source region and the second drain region.

公开(公告)号：US20170221884A1

公开(公告)日：2017-08-03

申请号：US15097142

申请日：2016-04-12

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Machkaoutsan ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  John Jianhong Zhu ,  Junjing Bao ,  Jeffrey Junhao Xu ,  Da Yang ,  Matthew Michael Nowak ,  Choh Fei Yeap

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/02

CPC classification number: H01L27/088 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/0207 ,  H01L27/0688 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0676 ,  H01L29/42392

Abstract: A device includes a substrate, a first nanowire field effect transistor (FET), and a second nanowire FET positioned between the substrate and the first nanowire FET. The device also includes a first nanowire electrically coupled to the first nanowire FET and to the second nanowire FET.

公开(公告)号：US20170170268A1

公开(公告)日：2017-06-15

申请号：US15367320

申请日：2016-12-02

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Peijie Feng ,  Kern Rim ,  Jeffrey Junhao Xu ,  Choh Fei Yeap

IPC: H01L29/06 ,  H01L21/324 ,  H01L27/088 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/02603 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/78696

Abstract: Nanowire metal-oxide semiconductor (MOS) Field-Effect Transistors (FETs) (MOSFETs) employing a nanowire channel structure having rounded nanowire structures is disclosed. To reduce the distance between adjacent nanowire structures to reduce parasitic capacitance while providing sufficient gate control of the channel, the nanowire channel structure employs rounded nanowire structures. For example, the rounded nanowire structures provide for a decreased height from a center area of the rounded nanowire structures to end areas of the rounded nanowire structures. Gate material is disposed around rounded ends of the rounded nanowire structures to extend into a portion of separation areas between adjacent nanowire structures. The gate material extends in the separation areas between adjacent nanowire structures sufficient to create a fringing field to the channel where gate material is not adjacently disposed, to provide strong gate control of the channel even though gate material does not completely surround the rounded nanowire structures.

公开(公告)号：US09660649B2

公开(公告)日：2017-05-23

申请号：US14639755

申请日：2015-03-05

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Kern Rim ,  Choh Fei Yeap

IPC: H03L5/00 ,  H03K19/00 ,  H03K19/0185 ,  G06F1/32 ,  G06F17/50

CPC classification number: H03K19/0016 ,  G06F1/3206 ,  G06F1/3212 ,  G06F1/3296 ,  G06F17/505 ,  G06F2209/5019 ,  G06F2217/68 ,  G06F2217/78 ,  H03K19/018507 ,  Y02D10/172 ,  Y02D10/174

Abstract: A method for scaling voltages provided to different modules of a system-on-chip (SOC) includes receiving, at an energy-performance engine of the SOC, a first indication of usage history for a first module of the SOC and a second indication of usage history for a second module of the SOC. The method includes receiving a battery life indication that indicates a remaining battery life for a battery of the SOC. The method also includes adjusting a first supply voltage provided to the first module of the SOC based on the first indication, the second indication, and the battery life indication. The method further includes adjusting a second supply voltage provided to the second module of the SOC based on the first indication, the second indication, and the battery life indication.

公开(公告)号：US20170110374A1

公开(公告)日：2017-04-20

申请号：US15198763

申请日：2016-06-30

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Stanley Seungchul Song ,  Da Yang ,  Vladimir Machkaoutsan ,  Mustafa Badaroglu ,  Choh Fei Yeap

IPC: H01L21/8238 ,  H01L29/78 ,  H01L21/02 ,  H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L29/04

CPC classification number: H01L21/823821 ,  H01L21/02118 ,  H01L21/022 ,  H01L21/823431 ,  H01L21/823807 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7853

Abstract: Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices are disclosed. In one aspect, an exemplary CMOS device includes a nanowire channel structure that includes a plurality of continuously stacked nanowires. Vertically adjacent nanowires are connected at narrow top and bottom end portions of each nanowire. Thus, the nanowire channel structure comprises a plurality of narrow portions that are narrower than a corresponding plurality of central portions. A wrap-around gate material is disposed around the nanowire channel structure, including the plurality of narrow portions, without entirely wrapping around any nanowire therein. The exemplary CMOS device provides, for example, a larger effective channel width and better gate control than a conventional fin field-effect transistor (FET) (FinFET) of a similar footprint. The exemplary CMOS device further provides, for example, a shorter nanowire channel structure than a conventional nanowire FET.