公开(公告)号：US20160124892A1

公开(公告)日：2016-05-05

申请号：US14533240

申请日：2014-11-05

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Joseph Robert Fitzgerald

IPC: G06F13/42 ,  G06F13/40 ,  G06F9/44 ,  G06F13/364

CPC classification number: G06F13/4282 ,  G06F9/4418 ,  G06F13/364 ,  G06F13/404 ,  H04L12/403 ,  Y02D10/14 ,  Y02D10/151

Abstract: Predefined static enumeration systems and processes for dynamic enumeration buses are disclosed. In one aspect, the dynamic enumeration bus may be a SOUNDWIRE™ bus. Slave devices are provided predefined device numbers which are provided to a master. The master uses the provided predefined device number to populate an address table. By providing the predefined device numbers, an iterative enumeration process may be reduced or eliminated, saving time and/or power.

Abstract translation: 公开了用于动态枚举总线的预定义静态枚举系统和过程。 在一个方面，动态枚举总线可以是SOUNDWIRE TM总线。 提供从设备提供给主设备的预定义设备号。 主机使用提供的预定义设备号填充地址表。 通过提供预定的设备编号，可以减少或消除迭代枚举过程，从而节省时间和/或功率。

公开(公告)号：US20160072492A1

公开(公告)日：2016-03-10

申请号：US14477367

申请日：2014-09-04

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Alexander Golubitski ,  Haim Hagay Haller ,  Felix Kolmakov ,  Gilad Sthoeger

IPC: H03K5/13 ,  G06F13/40 ,  G06F13/42 ,  G11C19/00

CPC classification number: H03K5/133 ,  G06F1/10 ,  G06F13/4068 ,  G06F13/4221 ,  G11C19/00 ,  H03K5/13 ,  H03K2005/0015 ,  Y02D10/14 ,  Y02D10/151

Abstract: Delay circuits, and related systems and methods are disclosed. In one aspect, a delay circuit is provided that uses logic to delay accurately an output enable signal to reduce or avoid data hazards within a slave device. The delay circuit includes two shift register chains configured to receive an output enable in signal based on a slow clock. A first shift register chain is clocked by a positive edge of a fast clock, and provides a first strobe signal. A second shift register chain is clocked by a negative edge of the fast clock, and provides a second strobe signal. The logic uses the first and second strobe signals, and the output enable in signal, to provide a delayed output enable out signal. The delay circuit provides a highly accurate time delay for the output enable signal to reduce or avoid data hazards in an area and power efficient manner.

Abstract translation: 公开了延迟电路及相关的系统和方法。 在一个方面，提供延迟电路，其使用逻辑来精确地延迟输出使能信号，以减少或避免从设备内的数据危害。 延迟电路包括两个移位寄存器链，其被配置为基于慢时钟接收信号中的输出使能。 第一移位寄存器链由快速时钟的上升沿提供时钟，并提供第一个选通信号。 第二移位寄存器链由快速时钟的负沿计时，并提供第二选通信号。 该逻辑使用第一和第二选通信号，以及信号中的输出使能，以提供延迟的输出使能输出信号。 延迟电路为输出使能信号提供高度准确的时间延迟，以减少或避免一个区域的数据危害和功率有效的方式。

公开(公告)号：US11843486B2

公开(公告)日：2023-12-12

申请号：US18055587

申请日：2022-11-15

Applicant: QUALCOMM Incorporated

Inventor： Tomer Rafael Ben-Chen ,  Sharon Graif ,  Lior Amarilio

IPC: H04L25/49 ,  H03K19/21 ,  H04B1/40 ,  H04L25/03 ,  H04W72/044

CPC classification number: H04L25/49 ,  H03K19/215 ,  H04B1/40 ,  H04L25/03866 ,  H04W72/0466

Abstract: High-speed communication links with self-aligned scrambling on a communication link that sends scrambled signals may include a slave device that may self-align by initially detecting an unscrambled preamble symbol and more particularly detect an edge of the unscrambled preamble symbol. Based on the detected edge, a fine alignment adjustment may be made by testing subsequent scrambled data for a repeated pattern such as an IDLE symbol by comparing the repeated pattern to a candidate scrambled sequence that has been received through the communication link. The comparison may use an exclusive OR (XOR) circuit on some bits to derive a scrambler seed that is used to test for a match for the remaining bits. If there is a match, the scrambler seed and frame alignment have been detected and alignment is achieved.

公开(公告)号：US20230076957A1

公开(公告)日：2023-03-09

申请号：US18055587

申请日：2022-11-15

Applicant: QUALCOMM Incorporated

Inventor： Tomer Rafael Ben-Chen ,  Sharon Graif ,  Lior Amarilio

IPC: H04L25/49 ,  H03K19/21 ,  H04L25/03 ,  H04B1/40 ,  H04W72/04

Abstract: High-speed communication links with self-aligned scrambling on a communication link that sends scrambled signals may include a slave device that may self-align by initially detecting an unscrambled preamble symbol and more particularly detect an edge of the unscrambled preamble symbol. Based on the detected edge, a fine alignment adjustment may be made by testing subsequent scrambled data for a repeated pattern such as an IDLE symbol by comparing the repeated pattern to a candidate scrambled sequence that has been received through the communication link. The comparison may use an exclusive OR (XOR) circuit on some bits to derive a scrambler seed that is used to test for a match for the remaining bits. If there is a match, the scrambler seed and frame alignment have been detected and alignment is achieved.

公开(公告)号：US10754607B2

公开(公告)日：2020-08-25

申请号：US16451553

申请日：2019-06-25

Applicant: QUALCOMM Incorporated

Inventor： Jason Gonzalez ,  Puxuan Dong ,  Lior Amarilio

IPC: G06F3/16 ,  H04R27/00 ,  H04L12/40 ,  G06F3/12 ,  H03M1/06 ,  H04L25/02 ,  H03K19/0185

Abstract: Systems and methods for multi-threshold sensing at an audio receiver, and systems and methods for calibrating an audio system to optimize for the specific configuration of the audio system are disclosed herein. In some implementations of a multi-threshold receiver, at least one additional voltage level is selected to trigger latching events within the receiver based on changes of the receiver input (which includes differential signals Vp and Vn) and in turn, to generate internal signals within the multi-threshold receiver, and then logic operations are performed on these internal signals to generate the output of the multi-threshold receiver.

公开(公告)号：US20200153593A1

公开(公告)日：2020-05-14

申请号：US16186961

申请日：2018-11-12

Applicant: QUALCOMM Incorporated

Inventor： Yiftach Benjamini ,  Shaul Yohai Yifrach ,  Lior Amarilio

IPC: H04L5/00 ,  G06F13/42 ,  H04L29/08 ,  H04L12/823 ,  H04L12/861

Abstract: Systems and methods for reducing latency on long distance point-to-point links where the point-to-point link is a Peripheral Component Interconnect (PCI) express (PCIE) link that modifies a receiver to advertise infinite or unlimited credits. A transmitter sends packets to the receiver. If the receiver's buffers fill, the receiver, contrary to PCIE doctrine, drops the packet and returns a negative acknowledgement (NAK) packet to the transmitter. The transmitter, on receipt of the NAK packet, resends packets beginning with the one for which the NAK packet was sent. By the time these resent packets arrive, the receiver will have had time to manage the packets in the buffers and be ready to receive the resent packets.

公开(公告)号：US20200089632A1

公开(公告)日：2020-03-19

申请号：US16134559

申请日：2018-09-18

Applicant: QUALCOMM Incorporated

Inventor： Sharon Graif ,  Lior Amarilio ,  Mark Gaknam

IPC: G06F13/24 ,  G06F13/362 ,  G06F13/42

Abstract: Systems, methods, and apparatus are described that enable communication of in-band reset signals over an I3C serial bus. A method performed at a slave device includes driving a data line of the I3C serial bus from a high state to a low state before a first clock pulse is received from a clock line of the I3C serial bus after a start condition has been provided on the I3C serial bus, where driving the data line from the high state to the low state produces an initial pulse on the data line, transmitting one or more additional pulses on the data line before the first clock pulse is transmitted on the clock line, and driving the data line low until a rising edge of the first clock pulse is detected on the clock line after each of the plurality of additional pulses has been successfully transmitted on the data line.

公开(公告)号：US20200073836A1

公开(公告)日：2020-03-05

申请号：US16115388

申请日：2018-08-28

Applicant: QUALCOMM Incorporated

Inventor： Sharon Graif ,  Lior Amarilio ,  Mark Gakman

IPC: G06F13/362 ,  G06F13/42 ,  G06F1/32 ,  G06F1/10

Abstract: Methods and apparatuses for operating a direct communication over a serial communication bus are provided. An apparatus includes a master having a host controller. The host controller is configured to communicate with a first slave and with a second slave via a serial communication bus using at least one master-slave address, in accordance with a serial communication protocol. The host controller includes a master-slave module configured to operate communication with the first slave and with the second slave via the serial communication bus in accordance with the serial communication protocol and be in a low-power mode while the first slave and the second slave are in a direct communication. The host controller includes an always-on module configured to, while the master-slave module is in the low-power mode, clock the serial communication bus for the direct communication.

公开(公告)号：US20200019523A1

公开(公告)日：2020-01-16

申请号：US16032238

申请日：2018-07-11

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Sharon Graif ,  Yiftach Benjamini

IPC: G06F13/362 ,  G06F3/16 ,  G06F13/40

Abstract: Delayed bank switch commands in an audio system such as a SOUNDWIRE audio system may have slaves that have had a delay register added to register banks for each data port. When a bank switch command is received, a slave consults the delay register and delays switching by a number of frames indicated in the delay register. Such delays may be used to prevent interpreting non-audio data as part of a data stream, particularly at start up and closure of audio streams. If an audio stream is active, the delay may be set to zero. By precluding the evaluation of non-audio data, audio artifacts may be avoided and a better user experience provided.

公开(公告)号：US10482056B2

公开(公告)日：2019-11-19

申请号：US15819641

申请日：2017-11-21

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Yuval Corey Hershko ,  Nir Strauss

IPC: G06F13/42 ,  G06F1/3287 ,  G06F15/78 ,  G06F13/364

Abstract: Systems and methods to transfer master duties to a slave on a communication bus are disclosed. A master of a communication bus determines that one or more slaves are capable of serving as a sub-master, including providing a clock signal and owning control information bits. Once that determination is made, the master may determine that processing within the master is not required for a particular activity on the bus. The master then alerts one such capable slave to prepare to assume sub-master duties. Once the slave confirms that the slave is ready to assume the sub-master duties, the master may transmit a handover frame on the bus, and the slave begins acting as a sub-master. The master may then enter a low-power state, which may promote power savings, reduce heat generation, and provide other advantages.