公开(公告)号：US20070013021A1

公开(公告)日：2007-01-18

申请号：US11157229

申请日：2005-06-20

申请人： Qingchun Zhang

发明人： Qingchun Zhang

IPC分类号： H01L29/00

CPC分类号： H01L29/7722 ,  H01L29/0692 ,  H01L29/8083

摘要： A semiconductor device includes a drift layer of a first conductivity type having a doping concentration and a conduction layer also of the first conductivity type on the drift layer that has a doping concentration greater than the doping concentration of the drift layer. The device also includes a pair of trench structures, each including a trench contact at one end and a region of a second conductivity type opposite the first conductivity type, at another end. Each trench structure extends into and terminates within the conduction layer such that the second-conductivity-type region is within the conduction layer. A first contact structure is on the drift layer opposite the conduction layer while a second contact structure is on the conduction layer.

摘要翻译： 半导体器件包括具有掺杂浓度的第一导电类型的漂移层和在漂移层上也具有大于漂移层的掺杂浓度的掺杂浓度的第一导电类型的导电层。 该装置还包括一对沟槽结构，每个沟槽结构在另一端包括在一端处的沟槽接触和与第一导电类型相反的第二导电类型的区域。 每个沟槽结构延伸到导电层内并终止于导电层，使得第二导电型区域在导电层内。 第一接触结构在与导电层相对的漂移层上，而第二接触结构在导电层上。

公开(公告)号：US09478537B2

公开(公告)日：2016-10-25

申请号：US12503386

申请日：2009-07-15

申请人： Qingchun Zhang ,  Anant K. Agarwal

发明人： Qingchun Zhang ,  Anant K. Agarwal

IPC分类号： H01L29/24 ,  H01L29/73 ,  H01L21/331 ,  H01L27/082 ,  H01L21/82 ,  H01L29/16

CPC分类号： H01L27/0825 ,  H01L21/8213 ,  H01L29/1608 ,  H01L29/73

摘要： A packaged power electronic device includes a wide bandgap bipolar driver transistor having a base, a collector, and an emitter terminal, and a wide bandgap bipolar output transistor having a base, a collector, and an emitter terminal. The collector terminal of the output transistor is coupled to the collector terminal of the driver transistor, and the base terminal of the output transistor is coupled to the emitter terminal of the driver transistor to provide a Darlington pair. An area of the output transistor is at least 3 times greater than an area of the driver transistor in plan view. For example, an area ratio of the output transistor to the driver transistor may be between about 3:1 to about 5:1. Related devices and methods of fabrication are also discussed.

摘要翻译： 封装的功率电子器件包括具有基极，集电极和发射极端子的宽带隙双极驱动晶体管，以及具有基极，集电极和发射极端子的宽带隙双极性输出晶体管。 输出晶体管的集电极端子耦合到驱动晶体管的集电极端子，并且输出晶体管的基极端子耦合到驱动晶体管的发射极端子以提供达林顿对。 在平面图中，输出晶体管的面积比驱动晶体管的面积至少大3倍。 例如，输出晶体管与驱动晶体管的面积比可以在约3:1至约5:1之间。 还讨论了相关装置和制造方法。

公开(公告)号：US09117739B2

公开(公告)日：2015-08-25

申请号：US12719412

申请日：2010-03-08

申请人： Qingchun Zhang

发明人： Qingchun Zhang

IPC分类号： H01L29/47 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66 ,  H01L29/861 ,  H01L29/872 ,  H01L29/06

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/861

摘要： An electronic device includes a silicon carbide layer including an n-type drift region therein, a contact forming a junction, such as a Schottky junction, with the drift region, and a p-type junction barrier region on the silicon carbide layer. The p-type junction barrier region includes a p-type polysilicon region forming a P-N heterojunction with the drift region, and the p-type junction barrier region is electrically connected to the contact. Related methods are also disclosed.

摘要翻译： 电子器件包括其中包括n型漂移区的碳化硅层，与漂移区形成诸如肖特基结的结的接触以及碳化硅层上的p型结阻挡区。 p型结屏障区域包括与漂移区域形成P-N异质结的p型多晶硅区域，并且p型结阻挡区域电连接到触点。 还公开了相关方法。

公开(公告)号：US08928108B2

公开(公告)日：2015-01-06

申请号：US12719412

申请日：2010-03-08

申请人： Qingchun Zhang

发明人： Qingchun Zhang

IPC分类号： H01L29/47 ,  H01L29/872 ,  H01L29/06 ,  H01L29/165 ,  H01L29/861 ,  H01L29/16 ,  H01L29/66

摘要： An electronic device includes a silicon carbide layer including an n-type drift region therein, a contact forming a junction, such as a Schottky junction, with the drift region, and a p-type junction barrier region on the silicon carbide layer. The p-type junction barrier region includes a p-type polysilicon region forming a P-N heterojunction with the drift region, and the p-type junction barrier region is electrically connected to the contact. Related methods are also disclosed.

公开(公告)号：US20130032809A1

公开(公告)日：2013-02-07

申请号：US13605324

申请日：2012-09-06

申请人： Scott Thomas Allen ,  Qingchun Zhang

发明人： Scott Thomas Allen ,  Qingchun Zhang

IPC分类号： H01L29/06 ,  H01L21/329

CPC分类号： H01L29/1608 ,  H01L21/8213 ,  H01L29/0619 ,  H01L29/165 ,  H01L29/47 ,  H01L29/66068 ,  H01L29/861 ,  H01L29/872

摘要： An electronic device includes a silicon carbide layer including an n-type drift region therein, a contact forming a Schottky junction with the drift region, and a p-type junction barrier region on the silicon carbide layer. The p-type junction barrier region includes a p-type polysilicon region forming a P-N heterojunction with the drift region, and the p-type junction barrier region is electrically connected to the contact.

摘要翻译： 电子器件包括其中包含n型漂移区的碳化硅层，与漂移区形成肖特基结的接触以及碳化硅层上的p型结阻挡区。 p型结屏障区域包括与漂移区域形成P-N异质结的p型多晶硅区域，并且p型结阻挡区域电连接到触点。

公开(公告)号：US20100289032A1

公开(公告)日：2010-11-18

申请号：US12719497

申请日：2010-03-08

申请人： Qingchun Zhang ,  Anant K. Agarwal ,  Tangali S. Sudarshan ,  Alexander Bolotnikov

发明人： Qingchun Zhang ,  Anant K. Agarwal ,  Tangali S. Sudarshan ,  Alexander Bolotnikov

IPC分类号： H01L29/24 ,  H01L21/225

CPC分类号： H01L29/1608 ,  H01L21/0465 ,  H01L21/223 ,  H01L29/0615 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/36 ,  H01L29/8613 ,  H01L29/872

摘要： An electronic device includes a silicon carbide layer having a first conductivity type and a main junction adjacent a surface of the silicon carbide layer, and a junction termination region at the surface of the silicon carbide layer adjacent the main junction. Charge in the junction termination region decreases with lateral distance from the main junction, and a maximum charge in the junction termination region may be less than about 2×1014 cm−2.

摘要翻译： 电子器件包括具有第一导电类型的碳化硅层和邻近碳化硅层的表面的主结，以及邻近主结的碳化硅层表面处的结终端区。 连接终端区域中的电荷随着与主结的横向距离而减小，并且接合终端区域中的最大电荷可能小于约2×1014cm-2。

公开(公告)号：US20090072242A1

公开(公告)日：2009-03-19

申请号：US11857037

申请日：2007-09-18

申请人： Qingchun Zhang

发明人： Qingchun Zhang

IPC分类号： H01L29/739 ,  H01L21/331 ,  H01L29/24

CPC分类号： H01L29/1608 ,  H01L29/0603 ,  H01L29/66068 ,  H01L29/7395

摘要： Insulated gate bipolar conduction transistors (IBCTs) are provided. The IBCT includes a drift layer having a first conductivity type. An emitter well region is provided in the drift layer and has a second conductivity type opposite the first conductivity type. A well region is provided in the drift layer and has the second conductivity type. The well region is spaced apart from the emitter well region. A space between the emitter well region and the well region defines a JFET region of the IBCT. An emitter region is provided in the well region and has the first conductivity type and a buried channel layer is provided on the emitter well region, the well region and the JFET region and has the first conductivity type. Related methods of fabrication are also provided.

摘要翻译： 提供绝缘栅双极型导电晶体管（IBCT）。 IBCT包括具有第一导电类型的漂移层。 发射极阱区设置在漂移层中，并且具有与第一导电类型相反的第二导电类型。 阱区设置在漂移层中并且具有第二导电类型。 阱区域与发射极阱区域间隔开。 发射极阱区和阱区之间的空间限定了IBCT的JFET区。 发射极区域设置在阱区中并且具有第一导电类型，并且在发射极阱区，阱区和JFET区上设置掩埋沟道层并具有第一导电类型。 还提供了相关的制造方法。

公开(公告)号：US20080296771A1

公开(公告)日：2008-12-04

申请号：US11756020

申请日：2007-05-31

申请人： Mrinal Kanti Das ,  Qingchun Zhang ,  John M. Clayton, JR. ,  Matthew Donofrio

发明人： Mrinal Kanti Das ,  Qingchun Zhang ,  John M. Clayton, JR. ,  Matthew Donofrio

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L29/66068 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/268 ,  H01L23/4827 ,  H01L29/1095 ,  H01L29/7395 ,  H01L2224/04026 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

摘要： A silicon carbide power device is fabricated by forming a p-type silicon carbide epitaxial layer on an n-type silicon carbide substrate, and forming a silicon carbide power device structure on the p-type silicon carbide epitaxial layer. The n-type silicon carbide substrate is at least partially removed, so as to expose the p-type silicon carbide epitaxial layer. An ohmic contact is formed on at least some of the p-type silicon carbide epitaxial layer that is exposed. By at least partially removing the n-type silicon carbide substrate and forming an ohmic contact on the p-type silicon carbide epitaxial layer, the disadvantages of using a p-type substrate may be reduced or eliminated. Related structures are also described.

摘要翻译： 通过在n型碳化硅衬底上形成p型碳化硅外延层并在p型碳化硅外延层上形成碳化硅功率器件结构来制造碳化硅功率器件。 至少部分去除n型碳化硅衬底，以露出p型碳化硅外延层。 在露出的至少一些p型碳化硅外延层上形成欧姆接触。 通过至少部分去除n型碳化硅衬底并在p型碳化硅外延层上形成欧姆接触，可以减少或消除使用p型衬底的缺点。 还描述了相关结构。

公开(公告)号：US20080085591A1

公开(公告)日：2008-04-10

申请号：US11539482

申请日：2006-10-06

申请人： Mercedes P. Gomez ,  Emil M. Hanna ,  Wen-Ben Luo ,  Qingchun Zhang

发明人： Mercedes P. Gomez ,  Emil M. Hanna ,  Wen-Ben Luo ,  Qingchun Zhang

IPC分类号： H01L21/3205

CPC分类号： H01L29/8083 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/42316 ,  H01L29/4925 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/66909

摘要： In accordance with an embodiment of the present invention, a gate structure for a U-shape Metal-Oxide-Semiconductor (UMOS) device includes a dielectric layer formed into a U-shape having side walls and a floor to form a trench surrounding a dielectric layer interior region, a doped poly-silicon layer deposited adjacent to the dielectric layer within the dielectric layer interior region where the doped poly-silicon layer has side walls and a floor surrounding a doped poly-silicon layer interior region, a first metal layer deposited on the doped poly-silicon layer on a side opposite from the dielectric layer where the first metal layer has side walls and a floor surrounding a first metal layer interior region, and an undoped poly-silicon layer deposited to fill the first metal layer interior region.

摘要翻译： 根据本发明的实施例，用于U形金属氧化物半导体（UMOS）器件的栅极结构包括形成为具有侧壁和底板的U形的电介质层，以形成围绕电介质的沟槽 在介电层内部区域中与电介质层相邻沉积的掺杂多晶硅层，其中掺杂多晶硅层具有侧壁和围绕掺杂多晶硅层内部区域的底板，沉积的第一金属层 在与第一金属层具有侧壁的电介质层相对的一侧上的掺杂多晶硅层和围绕第一金属层内部区域的地板和沉积以填充第一金属层内部区域的未掺杂多晶硅层 。

公开(公告)号：US06475520B1

公开(公告)日：2002-11-05

申请号：US09787338

申请日：2001-03-16

申请人： Wanhui Liu ,  Qingchun Zhang ,  Shixu Li ,  Kajia Su ,  Shuyan Liu ,  Fabing Zhu

发明人： Wanhui Liu ,  Qingchun Zhang ,  Shixu Li ,  Kajia Su ,  Shuyan Liu ,  Fabing Zhu

IPC分类号： A61K920

CPC分类号： C07J53/00 ,  A61K31/56 ,  A61K31/70 ,  C07J63/00

摘要： The present invention relates to a pharmaceutical composition with low toxicity for anti-inflammatory and anti-exudative which contains as active ingredients escin with general formula I and escin with general formula II as well as pharmaceutically acceptable carrier or excipient. In comparison with ESCIN, this pharmaceutical composition possesses the same anti-inflammatory and anti-exudative activity, but both toxicity and irritation lower remarkably.

摘要翻译： 本发明涉及具有低抗毒性和抗渗透性的药物组合物，其含有通式Ⅰ的活性成分和通式II的七叶素以及药学上可接受的载体或赋形剂。 与ESCIN相比，该药物组合物具有相同的抗炎和抗渗血作用，但毒性和刺激性明显降低。