公开(公告)号：US06768335B1

公开(公告)日：2004-07-27

申请号：US10354520

申请日：2003-01-30

申请人： Steven P. Young ,  Michael J. Hart ,  Venu M. Kondapalli ,  Martin L. Voogel

发明人： Steven P. Young ,  Michael J. Hart ,  Venu M. Kondapalli ,  Martin L. Voogel

IPC分类号： G06F738

CPC分类号： H03K17/005 ,  H03K17/693 ,  H03K19/17736 ,  H03K19/1778

摘要： A multiplexer that can be used, for example, in a programmable logic device (PLD). The multiplexer includes a plurality of pass transistors passing a selected one of several input values to an internal node, which drives a buffer that provides the multiplexer output signal. The pass transistors can be controlled, for example, by values stored in memory cells of a PLD. The pass transistors have a first oxide thickness and are controlled by a value having a first operating voltage. The buffer includes transistors having a second and thinner oxide thickness, and is operated at a second and lower operating voltage. Where memory cells are used to control the pass transistors, the memory cells include transistors having the first oxide thickness and operate at the first operating voltage. Some embodiments also include transistors of varying gate length for each of the pass transistors, buffer transistors, and memory cell transistors.

摘要翻译： 可以用于例如可编程逻辑器件（PLD）中的多路复用器。 多路复用器包括将多个输入值中选择的一个输入值传送到内部节点的多个传输晶体管，驱动提供多路复用器输出信号的缓冲器。 可以例如通过存储在PLD的存储器单元中的值来控制传输晶体管。 传输晶体管具有第一氧化物厚度并且由具有第一工作电压的值控制。 缓冲器包括具有第二和较薄氧化物厚度的晶体管，并且在第二和较低工作电压下操作。 在使用存储器单元来控制传输晶体管的情况下，存储单元包括具有第一氧化物厚度并在第一工作电压下工作的晶体管。 一些实施例还包括用于每个传输晶体管，缓冲晶体管和存储单元晶体管的栅极长度变化的晶体管。

公开(公告)号：US06526557B1

公开(公告)日：2003-02-25

申请号：US09624818

申请日：2000-07-25

申请人： Steven P. Young ,  Trevor J. Bauer

发明人： Steven P. Young ,  Trevor J. Bauer

IPC分类号： G06F1750

CPC分类号： H03K19/17756

摘要： An FPGA architecture and method enables partial reconfiguration of selected configurable logic blocks (CLBs) connected to an address line without affecting other CLBs connected to the same address line. Partial reconfiguration at a memory cell resolution is achieved by manipulating the input voltages applied to the address and data lines of an FPGA so that certain memory cells are programmed while other memory cells are not programmed. In addition, partial reconfiguration at a CLB resolution can be achieved by hardwiring the FPGA to enable selection of individual CLBs for reconfiguration.

摘要翻译： FPGA架构和方法使得能够部分重新配置连接到地址线的所选择的可配置逻辑块（CLB），而不会影响连接到同一地址线的其他CLB。 通过操纵施加到FPGA的地址和数据线的输入电压来实现存储器单元分辨率的部分重新配置，使得某些存储器单元被编程而其他存储器单元未被编程。 此外，CLB分辨率的部分重新配置可以通过硬连线FPGA来实现，以便能够选择单个CLB进行重新配置。

公开(公告)号：US06445209B1

公开(公告)日：2002-09-03

申请号：US09566398

申请日：2000-05-05

申请人： Steven P. Young ,  Trevor J. Bauer ,  Richard A. Carberry

发明人： Steven P. Young ,  Trevor J. Bauer ,  Richard A. Carberry

IPC分类号： H03K19177

CPC分类号： H03K19/17728 ,  H03K19/1737

摘要： A fast, space-efficient lookup table (LUT) for programmable logic devices (PLDs) in which the write decoder, read decoder and memory block of the LUT are modified to improve performance while providing a highly efficient layout. Both the write decoder and the read decoder are controlled by LUT input signals, and data signals are transmitted directly to each memory circuit of the memory block (i.e., without passing through the write decoder). The write decoder includes NOR gates that generate select signals used to address individual memory circuits during write operations. For dynamic latching during reading or shifting, each memory circuit includes an inverter circuit connected between the memory cell and the output terminal of the memory circuit. The read decoder includes a multiplexing circuit made up of a series of 2-to-1 multiplexers that are directly controlled by the input signals received from the interconnect resources of the PLD. In one embodiment, a configurable logic block is provided with a single write decoder that is shared by a first LUT and a second LUT.

摘要翻译： 用于可编程逻辑器件（PLD）的快速，节省空间的查找表（LUT），其中修改LUT的写解码器，读取解码器和存储器块以提供高性能，同时提供高效布局。 写解码器和读取解码器都由LUT输入信号控制，数据信号被直接发送到存储器块的每个存储电路（即不经过写入解码器）。 写入解码器包括NOR门，其产生用于在写入操作期间寻址各个存储器电路的选择信号。 对于读取或移位期间的动态锁存，每个存储器电路包括连接在存储器单元和存储器电路的输出端之间的反相器电路。 读取解码器包括由从PLD的互连资源接收的输入信号直接控制的一系列2对1复用器组成的复用电路。 在一个实施例中，可配置逻辑块被提供有由第一LUT和第二LUT共享的单个写入解码器。

公开(公告)号：US06323681B1

公开(公告)日：2001-11-27

申请号：US09546305

申请日：2000-04-10

申请人： Roman Iwanczuk ,  Steven P. Young ,  David P. Schultz

发明人： Roman Iwanczuk ,  Steven P. Young ,  David P. Schultz

IPC分类号： H01L2500

CPC分类号： H03K19/17776 ,  H03K19/17748 ,  H03K19/1776

摘要： An FPGA configuration memory is divided into columnar frames each having a unique address. Configuration data is loaded into a configuration register, which transfers configuration data frame by frame in parallel. In a preferred embodiment, an input register, a shadow input register and a multiplexer array permit efficient configuration data transfer using a larger number of input bits than conventional FPGAs. A flexible external interface enables connection with bus sizes varying from a predetermined maximum width down to a selected fraction thereof. Configuration data transfer is made more efficient by using shadow registers to drive such data into memory cells on a frame-by-frame basis with a minimum of delay, and by employing a multiplexer array to exploit a wider configuration data transfer bus. The speed of configuration readback is made substantially equal to the rate of configuration data input by employing configuration register logic that supports bidirectional data transfer. Using the invention, a bit stream designed for an old device can be used for a new device having additional configuration memory cells.

摘要翻译： FPGA配置存储器被分成具有唯一地址的柱状帧。 配置数据被加载到配置寄存器中，并且并行传送配置数据。 在优选实施例中，输入寄存器，影子输入寄存器和多路复用器阵列允许使用比常规FPGA更大数量的输入位的有效配置数据传送。 灵活的外部接口使得能够连接到从预定最大宽度到其选定分数的总线大小。 通过使用影子寄存器以最小的延迟逐帧地将这样的数据驱动到存储器单元中，并且通过采用多路复用器阵列来利用更宽的配置数据传输总线，使配置数据传输更有效。 通过采用支持双向数据传输的配置寄存器逻辑，配置回读的速度基本上等于输入配置数据的速率。 使用本发明，为旧设备设计的比特流可以用于具有附加配置存储单元的新设备。

公开(公告)号：US06278290B1

公开(公告)日：2001-08-21

申请号：US09374490

申请日：1999-08-13

申请人： Steven P. Young

发明人： Steven P. Young

IPC分类号： H01L2500

CPC分类号： H03K19/17772 ,  H03K19/17736 ,  H03K19/17764 ,  H03K19/1778 ,  H03K19/17784

摘要： A PLD includes buffered interconnect resources and configurable logic circuits that are controlled by data stored in a configuration memory. Each buffer of the buffered interconnect resources includes a feedback pull-up transistor. To avoid crowbar current problems, a high voltage is transmitted to the input terminals of all buffers before configuration, thereby biasing all buffers into a high feedback voltage mode. In one embodiment, the high voltage is transmitted to the buffers using a global control signal that forces all output drivers to generate high output voltages, and then turning on all pass transistors of the interconnect resources to broadcast the high voltages to every buffer. After configuration, the global control signal is de-activated. In another embodiment, each buffer circuit includes a second pull-up device that is turned on at power-up to force all buffers into the high feedback mode. In this embodiment, all pass transistors of the interconnect resources are turned off before configuration. In yet another embodiment, another global control signal is transmitted to all state devices of the PLD at the beginning of a stand-by/reconfiguration mode. In response to the additional control signal, all state devices ignore subsequent signals from the interconnect resources until configuration is completed and all output drivers are returned to their pre-stand-by operation state.

摘要翻译： PLD包括由存储在配置存储器中的数据控制的缓冲互连资源和可配置逻辑电路。 缓冲互连资源的每个缓冲器包括反馈上拉晶体管。 为了避免电涌现象出现问题，高电压在配置之前传输到所有缓冲器的输入端，从而将所有缓冲器偏置为高反馈电压模式。 在一个实施例中，使用强制所有输出驱动器产生高输出电压的全局控制信号将高电压传输到缓冲器，然后接通互连资源的所有传输晶体管以将高电压广播到每个缓冲器。 配置完成后，全局控制信号被禁用。 在另一个实施例中，每个缓冲电路包括第二上拉装置，其在上电时导通，以迫使所有缓冲器进入高反馈模式。 在本实施例中，互连资源的全部通过晶体管在配置之前被关闭。 在另一个实施例中，在待机/重新配置模式开始时，另一个全局控制信号被发送到PLD的所有状态设备。 响应于附加控制信号，所有状态设备忽略来自互连资源的后续信号，直到配置完成并且所有输出驱动器返回到其待机前操作状态。

公开(公告)号：US06204695B1

公开(公告)日：2001-03-20

申请号：US09336357

申请日：1999-06-18

申请人： Peter H. Alfke ,  Alvin Y. Ching ,  Scott O. Frake ,  Jennifer Wong ,  Steven P. Young

发明人： Peter H. Alfke ,  Alvin Y. Ching ,  Scott O. Frake ,  Jennifer Wong ,  Steven P. Young

IPC分类号： H03H19096

CPC分类号： G06F1/10

摘要： A clock gating circuit is provided for a logic device that reduces device resource requirements, eliminates the need for users to define their own clock gating circuit, and eliminates undesirable clock signal disturbances, such as glitches and runt pulses. In one embodiment, the clock gating circuit includes an input terminal for receiving an input clock signal; an input terminal for receiving a clock enable signal; a storage latch coupled to receive the input clock signal and the clock enable signal, and in response, provide a clock gate control signal; and a logic gate coupled to receive the input clock signal and the clock gate control signal. The logic gate selectively routes the input clock signal in response to the clock gate control signal, thereby providing an output clock signal.

摘要翻译： 为逻辑器件提供时钟选通电路，可降低器件资源需求，消除用户定义自己的时钟选通电路的需要，并消除不期望的时钟信号干扰，如毛刺和欠压脉冲。 在一个实施例中，时钟选通电路包括用于接收输入时钟信号的输入端; 用于接收时钟使能信号的输入端; 存储锁存器，其耦合以接收所述输入时钟信号和所述时钟使能信号，并且作为响应，提供时钟门控制信号; 以及耦合以接收输入时钟信号和时钟门控制信号的逻辑门。 逻辑门选择地响应于时钟门控制信号路由输入时钟信号，由此提供输出时钟信号。

公开(公告)号：US06204691B1

公开(公告)日：2001-03-20

申请号：US09569745

申请日：2000-05-11

申请人： F. Erich Goetting ,  Scott O. Frake ,  Venu M. Kondapalli ,  Steven P. Young

发明人： F. Erich Goetting ,  Scott O. Frake ,  Venu M. Kondapalli ,  Steven P. Young

IPC分类号： H03K19094

CPC分类号： H03K19/17744 ,  H03K19/00361 ,  H03K19/1778 ,  H03K19/17788

摘要： The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.

摘要翻译： 本发明包括具有多个输入参考电压和/或输出电压源的FPGA。 在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。 根据本发明的第二方面，I / O焊盘线可配置地连接到输入参考电压线，使得可以使用任何可配置的输入/输出块（IOB）来提供输入参考电压。 根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。 根据本发明的另一方面，将单个输入参考电压和/或单个输出电压电源应用于每个IOB，其中IOB被分组成组。 每组IOB具有单独的输入参考电压和/或单独的输出电压电源。

公开(公告)号：US6137307A

公开(公告)日：2000-10-24

申请号：US128964

申请日：1998-08-04

申请人： Roman Iwanczuk ,  Steven P. Young

发明人： Roman Iwanczuk ,  Steven P. Young

IPC分类号： H03K19/177 ,  G06F7/38 ,  H03K19/173

CPC分类号： H03K19/17776 ,  H03K19/17748 ,  H03K19/17756 ,  H03K19/1776

摘要： An FPGA configuration memory is divided into columnar frames each having a unique address. Configuration data is loaded into a configuration register, which transfers configuration data frame by frame in parallel. In a preferred embodiment, an input register, a shadow input register and a multiplexer array permit efficient configuration data transfer using a larger number of input bits than conventional FPGAs. A flexible external interface enables connection with bus sizes varying from a predetermined maximum width down to a selected fraction thereof. Configuration data transfer is made more efficient by using shadow registers to drive such data into memory cells on a frame-by-frame basis with a minimum of delay, and by employing a multiplexer array to exploit a wider configuration data transfer bus. The speed of configuration readback is made substantially equal to the rate of configuration data input by employing configuration register logic that supports bidirectional data transfer. Using the invention, a bit stream designed for an old device can be used for a new device having additional configuration memory cells.

摘要翻译： FPGA配置存储器被分成具有唯一地址的柱状帧。 配置数据被加载到配置寄存器中，并且并行传送配置数据。 在优选实施例中，输入寄存器，影子输入寄存器和多路复用器阵列允许使用比常规FPGA更大数量的输入位的有效配置数据传送。 灵活的外部接口使得能够连接到从预定最大宽度到其选定分数的总线大小。 通过使用影子寄存器以最小的延迟逐帧地将这样的数据驱动到存储器单元中，并且通过采用多路复用器阵列来利用更宽的配置数据传输总线，使配置数据传输更有效。 通过采用支持双向数据传输的配置寄存器逻辑，配置回读的速度基本上等于输入配置数据的速率。 使用本发明，为旧设备设计的比特流可以用于具有附加配置存储单元的新设备。

公开(公告)号：US5920202A

公开(公告)日：1999-07-06

申请号：US835088

申请日：1997-04-04

申请人： Steven P. Young ,  Shekhar Bapat ,  Kamal Chaudhary ,  Trevor J. Bauer ,  Roman Iwanczuk

发明人： Steven P. Young ,  Shekhar Bapat ,  Kamal Chaudhary ,  Trevor J. Bauer ,  Roman Iwanczuk

IPC分类号： H01L25/00 ,  H03K19/173 ,  H03K19/177 ,  G06F7/38

CPC分类号： H03K19/17728 ,  H03K19/1737 ,  H03K19/17704

摘要： The invention provides a Configurable Logic Element (CLE) preferably included in each of an array of identical tiles. A CLE according to the invention has four function generators. The outputs of two function generators are combined with a fifth independent input in a five-input-function multiplexer or function generator to produce an output that can be any function of five inputs, or some functions of up to nine inputs. The outputs of the other two function generators are similarly combined. The outputs of the two five-input-function multiplexers or function generators are then combined with a sixth independent input in a first six-input-function multiplexer or function generator, and with a different sixth independent input in a second six-input-function multiplexer or function generator. The two six-input-function multiplexers or function generators therefore produce two outputs of which one can be any function of six inputs; the other output can be any function of six inputs provided that five inputs are shared between the two 6-input functions. Some functions of up to nineteen inputs can also be generated in a single CLE.

摘要翻译： 本发明提供了优选地包括在相同瓦片的阵列中的每一个中的可配置逻辑元件（CLE）。 根据本发明的CLE具有四个功能发生器。 两个功能发生器的输出与五输入功能多路复用器或函数发生器中的第五个独立输入组合，以产生可以是五个输入或多达九个输入的一些功能的输出。 其他两个功能发生器的输出类似地组合。 然后，两个五输入功能多路复用器或函数发生器的输出与第六个六输入函数多路复用器或函数发生器中的第六个独立输入组合，并在第六个六输入函数中与不同的第六独立输入进行组合 多路复用器或函数发生器。 因此，两个六输入功能多路复用器或函数发生器产生两个输出，其中一个可以是六个输入的任何功能; 另外的输出可以是六个输入的任何功能，只要在两个6输入功能之间共享五个输入。 也可以在单个CLE中生成多达十九个输入的某些功能。

公开(公告)号：US5914616A

公开(公告)日：1999-06-22

申请号：US806997

申请日：1997-02-26

申请人： Steven P. Young ,  Kamal Chaudhary ,  Trevor J. Bauer

发明人： Steven P. Young ,  Kamal Chaudhary ,  Trevor J. Bauer

IPC分类号： H01L25/00 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17796 ,  H03K19/1737 ,  H03K19/17704

摘要： The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length lines connecting to tiles several tiles away creates an interconnect hierarchy which allows any logic block to be connected to any other logic block, yet also allows for fast paths to both adjacent tiles and tiles some distance away. Longer interconnect lines may be included as a third level of hierarchy to permit interconnection of widely separated tiles. In a preferred embodiment, from a given tile an intermediate-length line connects to the tile three tiles away, then continues and connects to the tile six tiles away. In this embodiment, the intermediate-length line does not connect to the intervening tiles one, two, four, and five tiles away.

摘要翻译： 本发明提供了优选地包括在相同瓦片阵列中的FPGA互连结构。 连接到相邻瓦片的单条线和连接到瓦片几个瓦片的中间线的组合创建互连层级，其允许任何逻辑块连接到任何其他逻辑块，但是也允许到相邻瓦片的快速路径 和瓷砖有一段距离。 可以将更长的互连线包括为第三层次以允许广泛分隔的瓷砖的互连。 在优选实施例中，从给定的瓦片中，中间线连接到瓦片三瓦片，然后继续并连接到瓦片六瓦片。 在该实施例中，中间长度线不连接到中间瓦片一个，两个，四个和五个瓦片。