公开(公告)号：US07795121B2

公开(公告)日：2010-09-14

申请号：US12010937

申请日：2008-01-31

申请人： Tsunehiro Ino ,  Akio Kaneko ,  Nobutoshi Aoki

发明人： Tsunehiro Ino ,  Akio Kaneko ,  Nobutoshi Aoki

IPC分类号： H01L21/265

CPC分类号： H01L21/28202 ,  H01L21/268 ,  H01L21/2686 ,  H01L21/28035 ,  H01L21/2807 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/511 ,  H01L29/517

摘要： A method for manufacturing a semiconductor device is provided, which includes forming a gate insulating film on a semiconductor substrate, forming a first layer on the gate insulating film, the first layer containing a first p-type impurity and, an amorphous or polycrystalline formed of Si1-xGex (0≦x

摘要翻译： 提供一种制造半导体器件的方法，其包括在半导体衬底上形成栅极绝缘膜，在栅极绝缘膜上形成第一层，第一层包含第一p型杂质，以及由 Si1-xGex（0＆nlE; x <0.25），对第一层进行第一热处理，其中第一层在高于1100℃的温度下加热1毫秒以下，在第一层上形成第二层， 所述第二层包含第二p型杂质并由非晶硅或多晶硅形成，所述第二p型杂质的共价键半径小于所述第一p型杂质，并且使所述第二层经受第二加热 处理以在800℃至1100℃的温度下加热第二层。

公开(公告)号：US20100207188A1

公开(公告)日：2010-08-19

申请号：US12662590

申请日：2010-04-23

申请人： Nobutoshi Aoki ,  Hiroshi Akahori

发明人： Nobutoshi Aoki ,  Hiroshi Akahori

IPC分类号： H01L29/788

CPC分类号： H01L29/42336 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114

摘要： A semiconductor device according to an embodiment of the present invention includes: a semiconductor substrate; an isolation structure formed in a trench, formed in the semiconductor substrate, through a semiconductor oxide film; a floating gate formed on the semiconductor substrate between the isolation structures through an insulating film; a gate oxidation protection film formed on a side surface, on the isolation structure side, of the floating gate so that each of a part of a side surface and a bottom surface of the gate oxidation protection film contacts the insulating film; and a control gate formed on the floating gate through an inter-gate insulating film.

摘要翻译： 根据本发明实施例的半导体器件包括：半导体衬底; 形成在半导体衬底中的半导体氧化膜形成在沟槽中的隔离结构; 通过绝缘膜形成在隔离结构之间的半导体衬底上的浮动栅极; 栅极氧化保护膜，形成在浮置栅极的隔离结构侧的侧表面上，使得栅极氧化保护膜的侧面和底面的一部分与绝缘膜接触; 以及通过栅极间绝缘膜形成在浮置栅极上的控制栅极。

公开(公告)号：US20100207187A1

公开(公告)日：2010-08-19

申请号：US12644821

申请日：2009-12-22

申请人： Nobutoshi Aoki ,  Masaki Kondo ,  Takashi Izumida

发明人： Nobutoshi Aoki ,  Masaki Kondo ,  Takashi Izumida

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L29/40114

摘要： A nonvolatile semiconductor memory device comprises a memory cell. The memory cell includes a first gate insulating film formed on a semiconductor substrate, a floating gate formed on the first gate insulating film, a second gate insulating film formed on the floating gate, and a control gate formed on the second gate insulating film. The floating gate includes a first semiconductor film which contacts the first gate insulating film, and a metal film stacked on the semiconductor film. An effective tunneling thickness between the semiconductor substrate and the floating gate in a read operation is thicker than an effective tunneling thickness between the semiconductor substrate and the floating in a write operation.

摘要翻译： 非易失性半导体存储器件包括存储器单元。 存储单元包括形成在半导体衬底上的第一栅极绝缘膜，形成在第一栅极绝缘膜上的浮置栅极，形成在浮置栅极上的第二栅极绝缘膜，以及形成在第二栅极绝缘膜上的控制栅极。 浮置栅极包括与第一栅极绝缘膜接触的第一半导体膜和层叠在半导体膜上的金属膜。 在读取操作中，半导体衬底和浮置栅极之间的有效隧道厚度比在半导体衬底和写入操作中浮动之间的有效隧穿厚度厚。

公开(公告)号：US20100123184A1

公开(公告)日：2010-05-20

申请号：US12618119

申请日：2009-11-13

申请人： Takashi Izumida ,  Nobutoshi Aoki

发明人： Takashi Izumida ,  Nobutoshi Aoki

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/0688 ,  H01L27/11578 ,  H01L27/11582

摘要： In a nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors, each of the memory cell transistors of a charge trap type are at least composed of a first insulating layer and a first gate electrode respectively, and the select transistor is at least composed of a second insulating layer and a second gate electrode. The first gate electrode is provided with a first silicide layer of a first width formed on the first insulating layer. The second gate electrode is provided with an impurity-doped silicon layer formed on the second insulating layer and with a second silicide layer of a second width formed on the impurity-doped silicon layer. The second silicide has the same composition as the first silicide. The second width is larger than the first width.

摘要翻译： 在设置有沿方向排列的存储单元晶体管和选择晶体管以选择存储单元晶体管的非易失性半导体存储器件中，电荷陷阱型的每个存储单元晶体管至少由第一绝缘层和第一栅极 电极，并且选择晶体管至少由第二绝缘层和第二栅电极组成。 第一栅电极设置有形成在第一绝缘层上的第一宽度的第一硅化物层。 第二栅电极设置有形成在第二绝缘层上的杂质掺杂硅层，以及形成在杂质掺杂硅层上的第二宽度的第二硅化物层。 第二硅化物具有与第一硅化物相同的组成。 第二宽度大于第一宽度。

公开(公告)号：US07629243B2

公开(公告)日：2009-12-08

申请号：US11487994

申请日：2006-07-18

申请人： Tsunehiro Ino ,  Akio Kaneko ,  Nobutoshi Aoki

发明人： Tsunehiro Ino ,  Akio Kaneko ,  Nobutoshi Aoki

IPC分类号： H01L21/4763

CPC分类号： H01L21/28202 ,  H01L21/268 ,  H01L21/2686 ,  H01L21/28035 ,  H01L21/2807 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/511 ,  H01L29/517

摘要： A method for manufacturing a semiconductor device is provided, which includes forming a gate insulating film on a semiconductor substrate, forming a first layer on the gate insulating film, the first layer containing a first p-type impurity and, an amorphous or polycrystalline formed of Si1-xGex (0≦x

摘要翻译： 提供一种制造半导体器件的方法，其包括在半导体衬底上形成栅极绝缘膜，在栅极绝缘膜上形成第一层，第一层包含第一p型杂质，以及由 Si1-xGex（0 <= x <0.25），对第一层进行第一热处理，其中第一层在高于1100℃的温度下加热1毫秒以下，在第一层上形成第二层 所述第二层包含第二p型杂质并由非晶硅或多晶硅形成，所述第二p型杂质的共价键半径小于所述第一p型杂质的半值，并且使所述第二层经受第二层 热处理以在800℃至1100℃的温度下加热第二层。

公开(公告)号：US20080073697A1

公开(公告)日：2008-03-27

申请号：US11902752

申请日：2007-09-25

申请人： Nobutoshi Aoki ,  Hiroshi Akahori

发明人： Nobutoshi Aoki ,  Hiroshi Akahori

IPC分类号： H01L29/788 ,  H01L21/762

CPC分类号： H01L29/42336 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521

摘要： A semiconductor device according to an embodiment of the present invention includes: a semiconductor substrate; an isolation structure formed in a trench, formed in the semiconductor substrate, through a semiconductor oxide film; a floating gate formed on the semiconductor substrate between the isolation structures through an insulating film; a gate oxidation protection film formed on a side surface, on the isolation structure side, of the floating gate so that each of a part of a side surface and a bottom surface of the gate oxidation protection film contacts the insulating film; and a control gate formed on the floating gate through an inter-gate insulating film.

摘要翻译： 根据本发明实施例的半导体器件包括：半导体衬底; 形成在半导体衬底中的半导体氧化膜形成在沟槽中的隔离结构; 通过绝缘膜形成在隔离结构之间的半导体衬底上的浮动栅极; 栅极氧化保护膜，形成在浮置栅极的隔离结构侧的侧表面上，使得栅极氧化保护膜的侧面和底面的一部分与绝缘膜接触; 以及通过栅极间绝缘膜形成在浮置栅极上的控制栅极。

公开(公告)号：US20070164360A1

公开(公告)日：2007-07-19

申请号：US11645806

申请日：2006-12-27

申请人： Tetsu Morooka ,  Makoto Fujiwara ,  Nobutoshi Aoki

发明人： Tetsu Morooka ,  Makoto Fujiwara ,  Nobutoshi Aoki

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/26586 ,  H01L21/82385 ,  H01L21/823878 ,  H01L21/84

摘要： A semiconductor device has a supporting substrate applied with a predetermined potential, an insulating layer formed on the supporting substrate, a semiconductor layer formed on the insulating layer, a FDSOI transistor formed on the semiconductor layer and including a source region, a drain region, and a channel region, the channel region being formed between the source region and the drain region, and a high-concentration impurity region formed in a vicinity of a surface of the supporting substrate at least just below the channel region, in which an average impurity concentration in the vicinity of the surface of the supporting substrate just below the channel region is not lower than an impurity concentration of the channel region.

摘要翻译： 半导体器件具有施加预定电位的支撑衬底，形成在支撑衬底上的绝缘层，形成在绝缘层上的半导体层，形成在半导体层上的FDSOI晶体管，包括源极区，漏极区和 沟道区域，形成在源区域和漏极区域之间的沟道区域以及形成在支撑衬底的表面附近的至少刚好在沟道区域附近的高浓度杂质区域，其中平均杂质浓度 在沟道区正下方的支撑基板的表面附近，不低于沟道区域的杂质浓度。

公开(公告)号：US07186598B2

公开(公告)日：2007-03-06

申请号：US11103470

申请日：2005-04-12

申请人： Jun Yamauchi ,  Nobutoshi Aoki

发明人： Jun Yamauchi ,  Nobutoshi Aoki

IPC分类号： H01L21/00 ,  H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/2652

摘要： A semiconductor device having a semiconductor layer, includes: a first impurity atom having a covalent bond radius larger than a minimum radius of a covalent bond of a semiconductor constituent atom of a semiconductor layer; and a second impurity atom having a covalent bond radius smaller than a maximum radius of the covalent bond of the semiconductor constituent atom; wherein the first and second impurity atoms are arranged in a nearest neighbor lattice site location and at least one of the first and second impurity atoms is electrically active.

摘要翻译： 具有半导体层的半导体器件包括：具有大于半导体层半导体构成原子的共价键的最小半径的共价键半径的第一杂质原子; 和具有小于半导体组成原子的共价键的最大半径的共价键半径的第二杂质原子; 其中所述第一和第二杂质原子布置在最近的相邻晶格位置位置，并且所述第一和第二杂质原子中的至少一个是电活性的。

公开(公告)号：US20060278940A1

公开(公告)日：2006-12-14

申请号：US11287192

申请日：2005-11-28

申请人： Koichi Kato ,  Daisuke Matsushita ,  Koichi Muraoka ,  Yasushi Nakasaki ,  Yuichiro Mitani ,  Nobutoshi Aoki

发明人： Koichi Kato ,  Daisuke Matsushita ,  Koichi Muraoka ,  Yasushi Nakasaki ,  Yuichiro Mitani ,  Nobutoshi Aoki

IPC分类号： H01L29/94

CPC分类号： H01L29/16 ,  H01L21/28176 ,  H01L21/28185 ,  H01L29/518

摘要： A semiconductor device includes a semiconductor substrate; an insulation film provided on the semiconductor substrate; and an electrode provided on the insulation film, and containing boron and a semiconductor material, wherein at least one element of the group V and carbon is introduced into an interface between the insulation film and the electrode.

摘要翻译： 半导体器件包括半导体衬底; 设置在所述半导体基板上的绝缘膜; 以及设置在所述绝缘膜上并且含有硼和半导体材料的电极，其中所述V族和碳族中的至少一种元素被引入到所述绝缘膜和所述电极之间的界面中。