公开(公告)号：US06930360B2

公开(公告)日：2005-08-16

申请号：US10609392

申请日：2003-07-01

申请人： Jun Yamauchi ,  Nobutoshi Aoki

发明人： Jun Yamauchi ,  Nobutoshi Aoki

IPC分类号： H01L21/24 ,  H01L21/22 ,  H01L21/265 ,  H01L21/336 ,  H01L21/425 ,  H01L27/148 ,  H01L29/12 ,  H01L29/772 ,  H01L29/78 ,  A01L29/72

CPC分类号： H01L29/6659 ,  H01L21/2652

摘要： A semiconductor device having a semiconductor layer, includes: a first impurity atom having a covalent bond radius larger than a minimum radius of a covalent bond of a semiconductor constituent atom of a semiconductor layer; and a second impurity atom having a covalent bond radius smaller than a maximum radius of the covalent bond of the semiconductor constituent atom; wherein the first and second impurity atoms are arranged in a nearest neighbor lattice site location and at least one of the first and second impurity atoms is electrically active.

摘要翻译： 具有半导体层的半导体器件包括：具有大于半导体层半导体构成原子的共价键的最小半径的共价键半径的第一杂质原子; 和具有小于半导体组成原子的共价键的最大半径的共价键半径的第二杂质原子; 其中所述第一和第二杂质原子布置在最近的相邻晶格位置位置，并且所述第一和第二杂质原子中的至少一个是电活性的。

公开(公告)号：US07186598B2

公开(公告)日：2007-03-06

申请号：US11103470

申请日：2005-04-12

申请人： Jun Yamauchi ,  Nobutoshi Aoki

发明人： Jun Yamauchi ,  Nobutoshi Aoki

IPC分类号： H01L21/00 ,  H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/2652

摘要： A semiconductor device having a semiconductor layer, includes: a first impurity atom having a covalent bond radius larger than a minimum radius of a covalent bond of a semiconductor constituent atom of a semiconductor layer; and a second impurity atom having a covalent bond radius smaller than a maximum radius of the covalent bond of the semiconductor constituent atom; wherein the first and second impurity atoms are arranged in a nearest neighbor lattice site location and at least one of the first and second impurity atoms is electrically active.

摘要翻译： 具有半导体层的半导体器件包括：具有大于半导体层半导体构成原子的共价键的最小半径的共价键半径的第一杂质原子; 和具有小于半导体组成原子的共价键的最大半径的共价键半径的第二杂质原子; 其中所述第一和第二杂质原子布置在最近的相邻晶格位置位置，并且所述第一和第二杂质原子中的至少一个是电活性的。

公开(公告)号：US08686488B2

公开(公告)日：2014-04-01

申请号：US13602634

申请日：2012-09-04

申请人： Masaki Kondo ,  Nobutoshi Aoki ,  Takashi Izumida ,  Tomomi Yoda

发明人： Masaki Kondo ,  Nobutoshi Aoki ,  Takashi Izumida ,  Tomomi Yoda

IPC分类号： H01L29/788 ,  H01L21/4763

CPC分类号： H01L29/788 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/7883

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a floating gate electrode formed on the gate insulating film, made of polysilicon containing a p-type impurity as a group XIII element, and having a lower film and an upper film stacked on the lower film, an inter-electrode insulating film formed on the floating gate electrode, and a control gate electrode formed on the inter-electrode insulating film. One of a concentration and an activation concentration of the p-type impurity in the upper film is higher than one of a concentration and an activation concentration of the p-type impurity in the lower film.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括半导体衬底，形成在半导体衬底上的栅绝缘膜，形成在栅极绝缘膜上的浮栅，由含有p型杂质的多晶硅组成， 并且具有层叠在下膜上的下膜和上膜，形成在浮栅上的电极间绝缘膜和形成在电极间绝缘膜上的控制栅电极。 上膜中的p型杂质的浓度和活化浓度之一高于下膜中的p型杂质的浓度和活化浓度之一。

公开(公告)号：US08420467B2

公开(公告)日：2013-04-16

申请号：US13224449

申请日：2011-09-02

申请人： Takashi Izumida ,  Nobutoshi Aoki

发明人： Takashi Izumida ,  Nobutoshi Aoki

IPC分类号： H01L21/8224

CPC分类号： H01L29/7851 ,  H01L29/1054 ,  H01L29/66795

摘要： A semiconductor device has a semiconductor substrate, a semiconductor fin which is formed on the semiconductor substrate, which has a long side direction and a short side direction, and which has a carbon-containing silicon film including an impurity and a silicon film formed on the carbon-containing silicon film, a gate electrode which is formed to face both side surfaces of the semiconductor fin in the short side direction, source and drain regions which are respectively formed in the semiconductor fin located in the direction of both sides in the long side direction of the semiconductor fin so as to sandwich the gate electrode, and an element isolation insulating film which is formed on the side surface of the semiconductor fin and between the gate electrode and the semiconductor substrate.

摘要翻译： 半导体器件具有半导体衬底，形成在半导体衬底上的具有长边方向和短边方向的半导体鳍片，并且具有包含杂质的含碳硅膜和形成在其上的硅膜 含碳硅膜，形成为在短边方向上面对半导体翅片的两侧面的栅电极，分别形成在长边方向两侧的半导体翅片中的源区和漏区 半导体鳍片的方向以夹着栅极电极;以及元件隔离绝缘膜，其形成在半导体鳍片的侧表面上以及栅电极和半导体衬底之间。

公开(公告)号：US20100295112A1

公开(公告)日：2010-11-25

申请号：US12721757

申请日：2010-03-11

申请人： Takashi Izumida ,  Nobutoshi Aoki ,  Masaki Kondo ,  Takahisa Kanemura

发明人： Takashi Izumida ,  Nobutoshi Aoki ,  Masaki Kondo ,  Takahisa Kanemura

IPC分类号： H01L27/115

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883

摘要： A semiconductor storage device has a semiconductor substrate, a plurality of first insulating films formed on the semiconductor substrate with predetermined spacing therebetween, an element isolation region formed between the first insulating films in a first direction, a floating gate electrode comprising a first charge accumulation film formed on the first insulating film, a second charge accumulation film formed on the first charge accumulation film and having a width in a second direction orthogonal to the first direction smaller than the width of the first charge accumulation film, and a third charge accumulation film formed on the second charge accumulation film and having the width in the second direction larger than the width of the second charge accumulation film, a second insulating film formed on the second charge accumulation film and between the second charge accumulation film and the element isolation region, a third insulating film formed on the charge accumulation film and the element isolation region along the second direction, and a control gate electrode formed on the third insulating film.

摘要翻译： 半导体存储装置具有半导体基板，在半导体基板上形成有规定间隔的多个第一绝缘膜，在第一方向上形成在第一绝缘膜之间的元件隔离区域，包括第一电荷累积膜的浮栅电极 形成在所述第一绝缘膜上的第二电荷累积膜，形成在所述第一电荷累积膜上并且具有与所述第一方向正交的第二方向的宽度小于所述第一电荷累积膜的宽度的第二电荷累积膜，以及形成的第三电荷累积膜 在第二电荷累积膜上并且具有大于第二电荷累积膜的宽度的第二方向的宽度，形成在第二电荷累积膜上以及在第二电荷累积膜和元件隔离区之间的第二绝缘膜， 形成在电荷累积膜上的第三绝缘膜 和沿着第二方向的元件隔离区域，以及形成在第三绝缘膜上的控制栅极电极。

公开(公告)号：US07755134B2

公开(公告)日：2010-07-13

申请号：US11765881

申请日：2007-06-20

申请人： Masaru Kito ,  Nobutoshi Aoki ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaki Kondo ,  Naoki Kusunoki ,  Toshiyuki Enda ,  Sanae Ito ,  Hiroyoshi Tanimoto ,  Hideaki Aochi ,  Akihiro Nitayama ,  Riichiro Shirota

发明人： Masaru Kito ,  Nobutoshi Aoki ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaki Kondo ,  Naoki Kusunoki ,  Toshiyuki Enda ,  Sanae Ito ,  Hiroyoshi Tanimoto ,  Hideaki Aochi ,  Akihiro Nitayama ,  Riichiro Shirota

IPC分类号： H01L27/115

CPC分类号： H01L29/7881 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42336

摘要： A nonvolatile semiconductor memory device includes: a semiconductor region; device isolation regions placed in the semiconductor region and extending in a column direction; a semiconductor layer placed on the semiconductor region and between the device isolation regions, and having a convex shape in cross section along a row direction; source/drain regions placed in the semiconductor layer and spaced from each other; a gate insulating film placed on the semiconductor layer between the source/drain regions; a floating gate electrode layer placed on the gate insulating film; an intergate insulating film placed on the floating gate electrode layer and upper surfaces of the device isolation regions; and a control gate electrode layer placed on the intergate insulating film and extending in the row direction.

摘要翻译： 非易失性半导体存储器件包括：半导体区域; 器件隔离区域放置在半导体区域中并沿列方向延伸; 放置在半导体区域和器件隔离区之间的半导体层，沿着行方向具有凸形的横截面; 源极/漏极区域放置在半导体层中并彼此间隔开; 位于源极/漏极区之间的半导体层上的栅极绝缘膜; 放置在栅极绝缘膜上的浮栅电极层; 布置在浮栅电极层和器件隔离区的上表面上的隔间绝缘膜; 以及控制栅极电极层，其设置在所述隔间绝缘膜上并沿行方向延伸。

公开(公告)号：US20090101959A1

公开(公告)日：2009-04-23

申请号：US12248449

申请日：2008-10-09

申请人： Takahisa KANEMURA ,  Takashi Izumida ,  Nobutoshi Aoki

发明人： Takahisa KANEMURA ,  Takashi Izumida ,  Nobutoshi Aoki

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device including: a semiconductor substrate; memory cell transistors that are series-connected; and a select transistor that includes: a first diffusion region that is formed in the semiconductor substrate at one end of the memory cell transistors; a first insulating film that is formed on the semiconductor substrate at a side of the first diffusion region; a select gate electrode that is formed on the first insulating film; a semiconductor pillar that is formed to extend upward from the semiconductor substrate and to be separated from the select gate electrode; a second insulating film that is formed between the select gate electrode and the semiconductor pillar; and a second diffusion region that is formed on the semiconductor pillar.

摘要翻译： 根据本发明的一个方面，提供了一种非易失性半导体存储器件，包括：半导体衬底; 串联连接的存储单元晶体管; 以及选择晶体管，其包括：在所述存储单元晶体管的一端形成在所述半导体衬底中的第一扩散区域; 在所述第一扩散区域的一侧形成在所述半导体基板上的第一绝缘膜; 形成在所述第一绝缘膜上的选择栅电极; 形成为从半导体衬底向上延伸并与选择栅电极分离的半导体柱; 形成在选择栅电极和半导体柱之间的第二绝缘膜; 以及形成在所述半导体柱上的第二扩散区域。

公开(公告)号：US07459748B2

公开(公告)日：2008-12-02

申请号：US11549770

申请日：2006-10-16

申请人： Riichiro Shirota ,  Fumitaka Arai ,  Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Makoto Mizukami ,  Kiyotaka Miyano ,  Ichiro Mizushima

发明人： Riichiro Shirota ,  Fumitaka Arai ,  Toshiyuki Enda ,  Hiroyoshi Tanimoto ,  Naoki Kusunoki ,  Nobutoshi Aoki ,  Makoto Mizukami ,  Kiyotaka Miyano ,  Ichiro Mizushima

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor memory device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate with an insulating film interposed therebetween, the semiconductor layer being in contact with the semiconductor substrate via an opening formed in the insulating film; and a NAND cell unit formed on the semiconductor layer with a plurality of electrically rewritable and non-volatile memory cells connected in series and first and second select gate transistors disposed at both ends thereof.

摘要翻译： 半导体存储器件包括：半导体衬底; 在半导体衬底上形成有绝缘膜的半导体层，所述半导体层经由形成在所述绝缘膜中的开口与所述半导体衬底接触; 以及在半导体层上形成有串联连接的多个电可重写和非易失性存储单元的NAND单元单元，以及设置在其两端的第一和第二选择栅晶体管。

公开(公告)号：US07456096B2

公开(公告)日：2008-11-25

申请号：US11530724

申请日：2006-09-11

申请人： Takashi Yamauchi ,  Atsuhiro Kinoshita ,  Yoshinori Tsuchiya ,  Junji Koga ,  Koichi Kato ,  Nobutoshi Aoki ,  Kazuya Ohuchi

发明人： Takashi Yamauchi ,  Atsuhiro Kinoshita ,  Yoshinori Tsuchiya ,  Junji Koga ,  Koichi Kato ,  Nobutoshi Aoki ,  Kazuya Ohuchi

IPC分类号： H01L29/45

CPC分类号： H01L21/28537 ,  H01L21/265 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/41791 ,  H01L29/66143 ,  H01L29/66643 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7839 ,  H01L29/785 ,  H01L29/872 ,  H01L2029/7858

摘要： It is made possible to reduce the interface resistance at the interface between the nickel silicide film and the silicon. A semiconductor manufacturing method includes: forming an impurity region on a silicon substrate, with impurities being introduced into the impurity region; depositing a Ni layer so as to cover the impurity region; changing the surface of the impurity region into a NiSi2 layer through annealing; forming a Ni layer on the NiSi2 layer; and silicidating the NiSi2 layer through annealing.

摘要翻译： 可以降低硅化镍膜与硅之间界面处的界面电阻。 半导体制造方法包括：在硅衬底上形成杂质区域，杂质被引入杂质区域; 沉积Ni层以覆盖杂质区域; 通过退火将杂质区的表面改变成NiSi 2层; 在NiSi 2层上形成Ni层; 并通过退火对NiSi 2层进行硅化。

公开(公告)号：US20080246072A1

公开(公告)日：2008-10-09

申请号：US11773721

申请日：2007-07-05

申请人： Masaki Kondo ,  Takashi Izumida ,  Nobutoshi Aoki ,  Toshiharu Watanabe

发明人： Masaki Kondo ,  Takashi Izumida ,  Nobutoshi Aoki ,  Toshiharu Watanabe

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： In a nonvolatile semiconductor memory device including a memory cell column formed by connecting in series a plurality of memory cells each having a structure in which a charge-storage layer and a control gate are stacked via an insulating layer on a semiconductor substrate, a first selection transistor formed on the semiconductor substrate and connected between one end of the memory cell column and a common source line, and a second selection transistor formed on the semiconductor substrate and connected between the other end of the memory cell column and a bit line, a recessed portion is formed on a surface of the semiconductor substrate between the first selection transistor and a memory cell adjacent to the first selection transistor, and an edge at a side of the first selection transistor in the recessed portion reaches an end portion at a side of the memory cell in a gate of the first selection transistor.

摘要翻译： 在包括存储单元列的非易失性半导体存储器件中，该存储单元列是通过串联连接多个存储单元而形成的，每个存储单元具有通过绝缘层在半导体衬底上层叠电荷存储层和控制栅极的结构，第一选择 形成在半导体衬底上并连接在存储单元列的一端和公共源极线之间的晶体管，以及形成在半导体衬底上并连接在存储单元列的另一端和位线之间的第二选择晶体管， 部分形成在第一选择晶体管和与第一选择晶体管相邻的存储单元之间的半导体衬底的表面上，并且凹陷部分中的第一选择晶体管的一侧的边缘到达第二选择晶体管的一侧的端部 第一选择晶体管的栅极中的存储单元。