公开(公告)号：US20070013001A1

公开(公告)日：2007-01-18

申请号：US11182381

申请日：2005-07-15

申请人： Toshiharu Furukawa ,  Carl Radens ,  William Tonti ,  Richard Williams

发明人： Toshiharu Furukawa ,  Carl Radens ,  William Tonti ,  Richard Williams

IPC分类号： H01L27/12 ,  H01L27/01

CPC分类号： H01L29/045 ,  H01L21/76254 ,  H01L21/84 ,  H01L27/1203

摘要： The present invention provides an epitaxial imprinting process for fabricating a hybrid substrate that includes a bottom semiconductor layer; a continuous buried insulating layer present atop said bottom semiconductor layer; and a top semiconductor layer present on said continuous buried insulating layer, wherein said top semiconductor layer includes separate planar semiconductor regions that have different crystal orientations, said separate planar semiconductor regions are isolated from each other. The epitaxial printing process of the present invention utilizing epitaxial growth, wafer bonding and a recrystallization anneal.

摘要翻译： 本发明提供一种用于制造包括底部半导体层的混合衬底的外延压印工艺; 存在于所述底部半导体层顶部的连续掩埋绝缘层; 以及存在于所述连续掩埋绝缘层上的顶部半导体层，其中所述顶部半导体层包括具有不同晶体取向的分离的平面半导体区域，所述分开的平面半导体区域彼此隔离。 利用外延生长，晶片接合和再结晶退火的本发明的外延印刷方法。

公开(公告)号：US20060234428A1

公开(公告)日：2006-10-19

申请号：US11106004

申请日：2005-04-14

申请人： Toshiharu Furukawa ,  Carl Radens ,  William Tonti ,  Richard Williams

发明人： Toshiharu Furukawa ,  Carl Radens ,  William Tonti ,  Richard Williams

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L23/5252 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10S438/928 ,  H01L2924/00

摘要： Enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods are provided for implementing enhanced SOI BOX structures. An oxygen implant step is performed from a backside into a thinned silicon substrate layer. An anneal step forms thick buried oxide (BOX) regions from oxygen implants in the silicon substrate layer. The oxygen implant step forms an isolated region near the oxygen implants. A backside implant step selectively dopes the isolated region for forming a backgate for an SOI device being formed including a selected one of anti-fuse (AF) devices, and SOI transistors including PFET and NFET devices.

摘要翻译： 提供了增强的绝缘体上硅（SOI）掩埋氧化物（BOX）结构和方法来实现增强的SOI BOX结构。 将氧注入步骤从背面进行到薄化的硅衬底层。 退火步骤从硅衬底层中的氧注入形成厚的掩埋氧化物（BOX）区域。 氧注入步骤在氧植入物附近形成隔离区域。 背侧注入步骤选择性地掺杂用于形成包括所选择的抗熔丝（AF）器件的SOI器件的SOI器件的隔离区域以及包括PFET和NFET器件的SOI晶体管的隔离区域。

公开(公告)号：US20060060938A1

公开(公告)日：2006-03-23

申请号：US10948773

申请日：2004-09-23

申请人： Wagdi Abadeer ,  John Fifield ,  Robert Gauthier ,  William Tonti

发明人： Wagdi Abadeer ,  John Fifield ,  Robert Gauthier ,  William Tonti

IPC分类号： H01L29/00 ,  H01L21/44

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A resettable fuse device is fabricated on one surface of a semiconductor substrate (10) and includes: a gate region (20) having first and second ends; a source node (81) formed in proximity to the first end of the gate region; an extension region (52) formed to connect the source node to the first end of the gate region; and a drain node (80) formed in proximity to the second end of the gate region and separated from the gate region by a distance (D) such that upon application of a predetermined bias voltage to the drain node a connection between the drain node and the second end of the gate region is completed by junction depletion. A gate dielectric (30) and a gate electrode (40) are formed over the gate region. Current flows between the source node and the drain node when the predetermined bias is applied to both the drain node and the gate electrode.

摘要翻译： 在半导体衬底（10）的一个表面上制造可重置熔丝器件，并且包括：具有第一和第二端的栅极区域（20） 源极节点（81），其形成在所述栅极区域的第一端附近; 形成为将源极节点连接到栅极区域的第一端的延伸区域（52） 以及漏极节点（80），其形成在栅极区域的第二端附近，并且与栅极区分离距离（D），使得在向漏极节点施加预定的偏置电压时，漏极节点和 栅极区域的第二端通过结损耗完成。 栅极电介质（30）和栅电极（40）形成在栅极区域上方。 当预定偏压施加到漏极节点和栅电极时，电流在源节点和漏极节点之间流动。

公开(公告)号：US20050275054A1

公开(公告)日：2005-12-15

申请号：US10853800

申请日：2004-05-25

申请人： Zachary Berndlmaier ,  Edward Kiewra ,  Carl Radens ,  William Tonti

发明人： Zachary Berndlmaier ,  Edward Kiewra ,  Carl Radens ,  William Tonti

IPC分类号： G01K7/01 ,  H01L27/02 ,  H01L29/66 ,  H01L31/0392

CPC分类号： H01L27/0248 ,  G01K7/01 ,  H01L29/66992

摘要： A thermal monitor diode is provided that comprises a silicon thin film on an insulator mounted on a silicon substrate. An opening extends through the silicon thin film and through the insulator and partially into the silicon substrate and terminates at an end wall. A conductive material is disposed in the opening and extends to the end wall. The substrate has a P/N junction formed therein adjacent the end wall, and an insulating spacer material surrounds the conductive material and is sufficiently thin to allow temperature excursions in the silicon thin film to pass therethrough. The invention also contemplates a method of forming the diode.

摘要翻译： 提供一种热监测二极管，其包括安装在硅衬底上的绝缘体上的硅薄膜。 开口延伸穿过硅薄膜并穿过绝缘体并部分地延伸到硅衬底中并终止于端壁。 导电材料设置在开口中并延伸到端壁。 衬底具有邻近端壁形成的P / N结，并且绝缘间隔物材料围绕导电材料并且足够薄以允许硅薄膜中的温度偏移通过。 本发明还考虑了形成二极管的方法。

公开(公告)号：US20050199966A1

公开(公告)日：2005-09-15

申请号：US11098103

申请日：2005-04-04

申请人： Qiuyi Ye ,  William Tonti ,  Yujun Li

发明人： Qiuyi Ye ,  William Tonti ,  Yujun Li

IPC分类号： H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/088 ,  H01L27/092 ,  H01L27/108 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/10888 ,  H01L21/76897 ,  H01L27/10894

摘要： A dual work function semiconductor structure with borderless contact and method of fabricating the same are presented. The structure may include a field effect transistor (FET) having a substantially cap-free gate and a conductive contact to a diffusion adjacent to the cap-free gate, wherein the conductive contact is borderless to the gate. Because the structure is a dual work function structure, the conductive contact is allowed to extend over the cap-free gate without being electrically connected thereto.

摘要翻译： 提出了一种具有无边界接触的双功能半导体结构及其制造方法。 该结构可以包括具有基本无帽栅极的场效应晶体管（FET）和与无盖栅极相邻的扩散部的导电接触，其中导电触点与栅极无边界。 由于该结构是双重功能结构，所以允许导电接触件在无盖栅极上延伸而不与其电连接。

公开(公告)号：US08575718B2

公开(公告)日：2013-11-05

申请号：US13289529

申请日：2011-11-04

申请人： Michael J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  William Tonti

发明人： Michael J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  William Tonti

IPC分类号： H01L23/52 ,  H01L21/82

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.

摘要翻译： 本发明涉及电熔丝装置，更具体地说，涉及一种形成电熔丝装置的装置和方法，所述方法包括提供连接到第二导电层的第一导电层，所述第一和第二导电层由 阻挡层具有与第一导电层的第二扩散率不同的第一扩散率。 通过驱动电流通过电熔丝装置而在第一导电层中产生空隙。

公开(公告)号：US20120280356A1

公开(公告)日：2012-11-08

申请号：US13552695

申请日：2012-07-19

申请人： Wagdi W. Abadeer ,  Lilian Kamal ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert R. Robison ,  William Tonti

发明人： Wagdi W. Abadeer ,  Lilian Kamal ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert R. Robison ,  William Tonti

IPC分类号： H01L29/06

CPC分类号： H01L21/76232

摘要： A solution for alleviating variable parasitic bipolar leakages in scaled semiconductor technologies is described herein. Placement variation is eliminated for edges of implants under shallow trench isolation (STI) areas by creating a barrier to shield areas from implantation more precisely than with only a standard photolithographic mask. An annealing process expands the implanted regions such their boundaries align within a predetermined distance from the edge of a trench. The distances are proportionate for each trench and each adjacent isolation region.

摘要翻译： 本文描述了用于减小缩放半导体技术中的可变寄生双极性泄漏的解决方案。 在浅沟槽隔离（STI）区域下的植入物的边缘，通过与仅使用标准光刻掩模相比更加精确地产生屏蔽区域而不是植入屏蔽区域来消除放置变化。 退火处理使注入区域扩展，使其边界在与沟槽边缘预定距离内对齐。 距离对于每个沟槽和每个相邻的隔离区域是成比例的。

公开(公告)号：US20120049321A1

公开(公告)日：2012-03-01

申请号：US13289529

申请日：2011-11-04

申请人： Michael J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  William Tonti

发明人： Michael J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  William Tonti

IPC分类号： H01L23/525 ,  H01L21/326

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.

摘要翻译： 本发明涉及电熔丝装置，更具体地说，涉及一种形成电熔丝装置的装置和方法，所述方法包括提供连接到第二导电层的第一导电层，所述第一和第二导电层由 阻挡层具有与第一导电层的第二扩散率不同的第一扩散率。 通过驱动电流通过电熔丝装置而在第一导电层中产生空隙。

公开(公告)号：US07772649B2

公开(公告)日：2010-08-10

申请号：US12036325

申请日：2008-02-25

申请人： Kangguo Cheng ,  Louis C. Hsu ,  Jack A. Mandelman ,  Carl Radens ,  William Tonti

发明人： Kangguo Cheng ,  Louis C. Hsu ,  Jack A. Mandelman ,  Carl Radens ,  William Tonti

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78648

摘要： A masking layer is applied over a top semiconductor layer and patterned to expose in an opening a shallow trench isolation structure and a portion of a top semiconductor region within which a first source/drain region and a body is to be formed. Ions are implanted into a portion of a buried insulator layer within the area of the opening to form damaged buried insulator region. The shallow trench isolation structure is removed and the damaged buried insulator region is etched selective to undamaged buried insulator portions to form a cavity. A dielectric layer is formed on the sidewalls and the exposed bottom surface of the top semiconductor region and a back gate filling the cavity is formed. A contact is formed to provide an electrical bias to the back gate so that the electrical potential of the body and the first source/drain region is electrically modulated.

摘要翻译： 将掩模层施加在顶部半导体层上并且被图案化以在开口中暴露浅沟槽隔离结构以及要在其中形成第一源极/漏极区域和主体的顶部半导体区域的一部分。 将离子注入到开口区域内的埋入绝缘体层的一部分中以形成损坏的埋层绝缘体区域。 去除浅沟槽隔离结构，并且损坏的埋层绝缘体区域被选择性地蚀刻到未损坏的埋入绝缘体部分以形成空腔。 在顶部半导体区域的侧壁和暴露的底表面上形成介电层，并且形成填充空腔的背栅。 形成接触以向后栅极提供电偏压，使得主体和第一源极/漏极区域的电势被电调制。

公开(公告)号：US07521776B2

公开(公告)日：2009-04-21

申请号：US11618346

申请日：2006-12-29

申请人： Ethan H. Cannon ,  Toshiharu Furukawa ,  Charles Koburger, III ,  Jack A. Mandelman ,  William Tonti

发明人： Ethan H. Cannon ,  Toshiharu Furukawa ,  Charles Koburger, III ,  Jack A. Mandelman ,  William Tonti

IPC分类号： H01L29/04

CPC分类号： H01L27/1203 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1083

摘要： Novel semiconductor structures and methods are disclosed for forming a buried recombination layer underneath the bulk portion of a hybrid orientation technology by implanting at least one recombination center generating element to reduce single event upset rates in CMOS devices thereabove. The crystalline defects in the buried recombination layer caused by the recombination center generating elements are not healed even after a high temperature anneal and serve as recombination centers where holes and electrons generated by ionizing radiation are collected by. Multiple buried recombination layers may be formed. Optionally, one such layer may be biased with a positive voltage to prevent latchup by collecting electrons.

摘要翻译： 公开了新的半导体结构和方法，用于通过在至少一个复合中心产生元件上植入至少一个复合中心产生元件以减少上述CMOS器件中的单一事件镦粗率来在混合取向技术的本体部分之下形成掩埋复合层。 由复合中心产生元件引起的掩埋复合层中的晶体缺陷即使在高温退火之后也不会愈合，并且用作通过电离辐射产生的空穴和电子的复合中心。 可以形成多个掩埋复合层。 可选地，一个这样的层可以被正电压偏置以通过收集电子来阻止闭锁。