公开(公告)号：US11227663B2

公开(公告)日：2022-01-18

申请号：US17173023

申请日：2021-02-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kiyohiko Sakakibara ,  Ippei Yasuda ,  Ken Oowada ,  Masaaki Higashitani

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C11/56 ,  G11C16/34 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519

Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.

公开(公告)号：US11133297B2

公开(公告)日：2021-09-28

申请号：US16669888

申请日：2019-10-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kwang-Ho Kim ,  Masaaki Higashitani ,  Fumiaki Toyama ,  Akio Nishida

IPC: H01L25/18 ,  H01L23/00 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11573 ,  H01L25/00 ,  H01L27/11575 ,  H01L27/1157 ,  H01L23/48 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11529 ,  H01L23/522

Abstract: A memory-containing die includes a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads. A logic die includes a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers. The logic-side bonding pads includes a pad-level mesh structure electrically connected to a source power supply circuit within the peripheral circuitry and containing an array of discrete openings therethrough, and discrete logic-side bonding pads. The logic-side bonding pads are bonded to a respective one, or a respective subset, of the memory-side bonding pads. The pad-level mesh structure can be used as a component of a source power distribution network.

公开(公告)号：US11107516B1

公开(公告)日：2021-08-31

申请号：US16798686

申请日：2020-02-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Masaaki Higashitani

IPC: H01L27/1159 ,  G11C11/22 ,  H01L29/16 ,  H01L29/778

Abstract: A ferroelectric memory device includes a two-dimensional electron gas channel, a gate electrode, and a ferroelectric element located between the gate electrode and the two-dimensional electron gas channel.

公开(公告)号：US11101284B2

公开(公告)日：2021-08-24

申请号：US16224367

申请日：2018-12-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jayavel Pachamuthu ,  Hiroyuki Kinoshita ,  Masaaki Higashitani ,  Makoto Dei ,  Junji Oh

IPC: H01L27/11548 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L29/10 ,  H01L29/08 ,  H01L21/311 ,  H01L21/02 ,  H01L21/265 ,  H01L21/266 ,  H01L29/49 ,  H01L21/768 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11526 ,  H01L27/11573 ,  H01L21/822

Abstract: A method of forming a semiconductor structure includes providing a dopant species selected from carbon, boron, nitrogen or oxygen into an upper portion of a semiconductor region to form a doped etch stop semiconductor material portion over a remaining semiconductor material portion, forming an overlying material portion over the etch stop semiconductor material portion, etching through the overlying material portion by an etch process that removes the overlying material portion selective to a material of the etch stop semiconductor material portion, and depositing at least one fill material over the etch stop semiconductor material portion.

公开(公告)号：US11088116B2

公开(公告)日：2021-08-10

申请号：US16694438

申请日：2019-11-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chen Wu ,  Peter Rabkin ,  Masaaki Higashitani

IPC: H01L25/065 ,  H01L21/768 ,  H01L21/822 ,  H01L27/06 ,  H01L23/00 ,  H01L25/00

Abstract: A first semiconductor die includes first bonding pads. The first bonding pads include proximal bonding pads embedded within a first bonding dielectric layer and distal bonding pads having at least part of the sidewall that overlies the first bonding dielectric layer. A second semiconductor die includes second bonding pads. The second bonding pads are bonded to the proximal bonding pads and the distal bonding pads. The proximal bonding pads are bonded to a respective one of a first subset of the second bonding pads at a respective horizontal bonding interface and the distal bonding pads are bonded to a respective one of a second subset of the second bonding pads at a respective vertical bonding interface at the same time. Dielectric isolation structures may vertically extend through the second bonding dielectric layer of the second semiconductor die and contact the first bonding dielectric layer.

公开(公告)号：US11037908B2

公开(公告)日：2021-06-15

申请号：US16521849

申请日：2019-07-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chen Wu ,  Peter Rabkin ,  Yangyin Chen ,  Masaaki Higashitani

IPC: H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768

Abstract: A bonded assembly includes a first semiconductor die including a first substrate, first semiconductor devices located on the first substrate, first dielectric material layers located on the first semiconductor devices and embedding first metal interconnect structures, and first through-substrate via structures extending through the first substrate and contacting a respective first metal interconnect structure. Each of the first through-substrate via structures laterally surrounds a respective core cavity that contains a void or a dielectric fill material portion. The bonded assembly includes a second semiconductor die attached to the first semiconductor die, and including a second substrate, second semiconductor devices located on the second substrate, second dielectric material layers located on the second semiconductor devices and embedding second metal interconnect structures, and bonding pad structures electrically connected to a respective one of the second metal interconnect structures and bonded to a respective first through-substrate via structure.

公开(公告)号：US11004518B2

公开(公告)日：2021-05-11

申请号：US16456045

申请日：2019-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kiyohiko Sakakibara ,  Hiroki Yabe ,  Ken Oowada ,  Masaaki Higashitani

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  H01L27/11524 ,  H01L27/1157 ,  G11C16/34 ,  G11C11/56 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519

Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.

公开(公告)号：US20210065802A1

公开(公告)日：2021-03-04

申请号：US16551553

申请日：2019-08-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Kwang-Ho Kim ,  Masaaki Higashitani

IPC: G11C16/06 ,  G11C16/14 ,  G11C16/04 ,  G11C16/34 ,  G11C16/30 ,  H03H11/28

Abstract: A memory system is provided with technology for performing temperature dependent impedance mitigation, in addition to or instead of other techniques to compensate for differences in impedance. For example, the memory system comprises a plurality of non-volatile memory cells, a first pathway connected to the plurality of non-volatile memory cells, a second pathway connected to the plurality of non-volatile memory cells, and a control circuit connected to the first pathway and the second pathway. The control circuit is configured to compensate based on temperature for a temperature dependent impedance mismatch between the first pathway and the second pathway during a memory operation on the plurality of non-volatile memory cells.

公开(公告)号：US10818685B2

公开(公告)日：2020-10-27

申请号：US16141163

申请日：2018-09-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mohan Dunga ,  James Kai ,  Venkatesh P. Ramachandra ,  Piyush Dak ,  Luisa Lin ,  Masaaki Higashitani

IPC: G11C11/24 ,  H01L27/11578 ,  G11C16/28 ,  G11C16/24 ,  H01L27/1157 ,  G11C16/08 ,  H01L27/11565 ,  H01L27/11573 ,  G11C16/30

Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and an I/O interface. A portion of the memory die is used as a pool capacitor for the I/O interface.

公开(公告)号：US20200294909A1

公开(公告)日：2020-09-17

申请号：US16886695

申请日：2020-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Luisa Lin ,  Mohan Dunga ,  Venkatesh P. Ramachandra ,  Peter Rabkin ,  Masaaki Higashitani

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L49/02 ,  H01L27/11582

Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.