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    Three-dimensional semiconductor memory device
    61.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US11233042B2

    公开(公告)日：2022-01-25

    申请号：US16850493

    申请日：2020-04-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chanho Kim ,  Joo-Yong Park ,  Daeseok Byeon

    IPC: H01L25/18 ,  H01L27/11573 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11582 ,  H01L49/02 ,  H01L27/11565 ,  H01L23/00 ,  H01L27/11575

    Abstract: A three-dimensional semiconductor memory device, including a first chip and a second chip stacked on the first chip may be provided. The first chip may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs, and second contact plugs, and a passive device on and electrically connected to the second contact plugs. The second chip may include a second substrate including a cell array region and a contact region, which vertically overlap the second peripheral circuit region and the first peripheral circuit region of the first chip, respectively. The second chip may further include gate electrodes, and cell contact plugs disposed on the contact region of the second substrate and on end portions of the gate electrodes. The first passive device may be vertically between the gate electrodes and the second contact plugs and may include a first contact line.

    Memory device
    62.
    发明授权
    Memory device 有权

    公开(公告)号：US11120843B2

    公开(公告)日：2021-09-14

    申请号：US16816476

    申请日：2020-03-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jooyong Park ,  Chanho Kim ,  Daeseok Byeon

    IPC: H01L23/522 ,  G11C5/06 ,  G11C5/04 ,  G11C7/18

    Abstract: A memory device includes a first semiconductor chip including a memory cell array disposed on a first substrate, and a first bonding metal on a first uppermost metal layer of the first semiconductor chip, and a second semiconductor chip including circuit devices disposed on a second substrate and a second bonding metal on a second uppermost metal layer of the second semiconductor chip, the circuit devices providing a peripheral circuit operating the memory cell array. The first and second semiconductor chips are electrically connected to each other by the first bonding metal and the second bonding metal in a bonding area. A routing wire electrically connected to the peripheral circuit is disposed in one or both of the first and second uppermost metal layers and is disposed in a non-bonding area in which the first and second semiconductor chips are not electrically connected to each other.

    Non-volatile memory device
    63.
    发明授权
    Non-volatile memory device 有权

    公开(公告)号：US11087844B2

    公开(公告)日：2021-08-10

    申请号：US16944312

    申请日：2020-07-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chanho Kim ,  Kyunghwa Yun ,  Daeseok Byeon

    IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

    Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and vertically connected to the memory cell region. The memory cell region includes a plurality of word lines, a ground selection line in a layer on the word lines, a common source line in a layer on the ground selection line, a plurality of vertical pass transistors in the stair area, and a plurality of driving signal lines in the same layer as the common source line. The word lines form a stair shape in the stair area, and each of the vertical pass transistors is connected between a corresponding one of the word lines and a corresponding one of the driving signal lines.

    Nonvolatile memory device with first and second precharge circuit
    65.
    发明授权
    Nonvolatile memory device with first and second precharge circuit 有权

    公开(公告)号：US10102910B2

    公开(公告)日：2018-10-16

    申请号：US15806543

    申请日：2017-11-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ji-Sang Lee ,  Donghun Kwak ,  Daeseok Byeon ,  Chiweon Yoon

    IPC: G11C11/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/24 ,  G11C16/04 ,  G11C16/26

    Abstract: A nonvolatile memory includes a memory cell array, a row decoder circuit, and a page buffer circuit. The row decoder circuit applies a turn-on voltage to string selection lines, which are connected to string selection transistors of a selected memory block, at a first precharge operation in response to a write command received from an external device. The page buffer circuit applies, in response to the write command, a first voltage to bit lines, which are connected to the string selection transistors, through a first precharge circuit at the first precharge operation regardless of loaded data and applies the first voltage and a second voltage to the bit lines through a second precharge circuit at a second precharge operation based on the loaded data. During the first precharge operation, write data is loaded onto the page buffer circuit.

    Three-dimensional flash memory device including dummy word line
    66.
    发明授权
    Three-dimensional flash memory device including dummy word line 有权
    三维闪存设备包括虚拟字线

    公开(公告)号：US09496038B1

    公开(公告)日：2016-11-15

    申请号：US15091843

    申请日：2016-04-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Donghun Kwak ,  Sang-Wan Nam ,  Daeseok Byeon ,  Chiweon Yoon

    IPC: G11C16/04 ,  G11C16/28 ,  G11C16/26

    CPC classification number: G11C16/0483 ,  G11C7/14 ,  G11C8/14 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3418

    Abstract: A three-dimensional flash memory device includes a plurality of cell strings arranged in a direction perpendicular to a substrate. The three-dimensional flash memory includes a first dummy word line disposed between a ground selection line and a main word line, and a second dummy word line disposed between the main word line and a string selection line and being asymmetric with respect to the first dummy word line. Voltages of different levels are respectively applied to the first and second dummy word lines during a read operation.

    Abstract translation: 三维闪速存储器件包括沿垂直于衬底的方向布置的多个单元串。 三维闪存包括设置在地选择线和主字线之间的第一虚拟字线和设置在主字线和字串选择线之间的第二虚拟字线，并且相对于第一伪线不对称 字线。 在读取操作期间，不同电平的电压分别应用于第一和第二伪字线。

    Semiconductor device
    69.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12062628B2

    公开(公告)日：2024-08-13

    申请号：US18126996

    申请日：2023-03-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changbum Kim ,  Sunghoon Kim ,  Daeseok Byeon

    IPC: H01L21/00 ,  H01L23/528 ,  H01L23/60 ,  H01L27/092

    CPC classification number: H01L23/60 ,  H01L23/528 ,  H01L27/092

    Abstract: A semiconductor device includes a gate line extending in a first direction, parallel to an upper surface of a semiconductor substrate; a first active region including a first channel region disposed below the gate line and including a first conductivity-type impurity; a second active region disposed to be separated from the first active region in the first direction, including a second channel region disposed below the gate line, and including the first conductivity-type impurity; and a plurality of metal wirings disposed at a first height level above the semiconductor substrate, wherein at least one metal wiring, among the plurality of metal wirings, is directly electrically connected to the first active region, no metal wirings at the first height level are electrically connected to the second active region, and at least one metal wiring, among the plurality of metal wirings, is connected to receive a signal applied to the gate line.

    MEMORY DEVICE INCLUDING PASS TRANSISTOR CIRCUIT
    70.
    发明公开
    MEMORY DEVICE INCLUDING PASS TRANSISTOR CIRCUIT 审中-公开

    公开(公告)号：US20240071517A1

    公开(公告)日：2024-02-29

    申请号：US18504093

    申请日：2023-11-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seungyeon Kim ,  Daeseok Byeon ,  Pansuk Kwak ,  Hongsoo Jeon

    IPC: G11C16/24 ,  G11C5/06 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

    CPC classification number: G11C16/24 ,  G11C5/06 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

    Abstract: A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.

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