公开(公告)号：US11698410B2

公开(公告)日：2023-07-11

申请号：US17471763

申请日：2021-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunhye Oh ,  Hyochul Shin ,  Jinwoo Park ,  Sungno Lee ,  Younghyo Park ,  Yongki Lee ,  Heejune Lee ,  Youngjae Cho ,  Michael Choi

IPC: G01R31/28 ,  H03K5/24 ,  H03M1/12

CPC classification number: G01R31/2884 ,  H03K5/24 ,  H03M1/124

Abstract: A test method is provided to test a semiconductor integrated circuit including an analog-to-digital converter and/or a digital-to-analog converter. An analog test signal having a test pattern is generated using an analog test signal generator or a digital test signal having the test pattern using a digital test signal generator. An analog output signal corresponding to the test pattern is generated by applying, as a digital input signal, the digital test signal having the test pattern to a digital-to-analog converter responsive to generation of the digital test signal. A digital output signal corresponding to the test pattern is generated by applying, as an analog input signal, the analog test signal having the test pattern or the analog output signal corresponding to the test pattern to an analog-to-digital converter. A normality of the semiconductor integrated circuit is determined based on the digital output signal corresponding to the test pattern.

公开(公告)号：US11587906B2

公开(公告)日：2023-02-21

申请号：US17168238

申请日：2021-02-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Park ,  Unbyoung Kang ,  Jongho Lee ,  Teakhoon Lee

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/16 ,  H01L23/31 ,  H01L23/00

Abstract: A package structure includes a lower substrate, substrate connection terminals on the lower substrate, a semiconductor package on the substrate connection terminals, the semiconductor package including a package substrate and a first encapsulant covering the package substrate, first underfills between the lower substrate and the semiconductor package, the first underfills covering corner portions of the semiconductor package, as viewed in a plan view, and covering at least one of the substrate connection terminals, and a second underfill between the lower substrate and the semiconductor package, the second underfill covering a side surface of the semiconductor package in a plan view.

公开(公告)号：US20230042622A1

公开(公告)日：2023-02-09

申请号：US17742819

申请日：2022-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Jihwang Kim ,  Jongbo Shim ,  Jinwoo Park

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a first package substrate having a lower surface and an upper surface respectively including a plurality of first lower surface pads and a plurality of first upper surface pads, a second package substrate having a lower surface and an upper surface respectively including a plurality of second lower surface pads and a plurality of second upper surface pads, wherein the plurality of second upper surface pads comprise all of the upper surface pads at the upper surface of the second package substrate, a semiconductor chip provided between the first package substrate and the second package substrate and attached onto the first package substrate, and a plurality of metal core structures connecting some of the plurality of first upper surface pads to some of the plurality of second lower surface pads and not vertically overlapping any of the plurality of second upper surface pads, each metal core structure having a metal core.

公开(公告)号：US11568903B2

公开(公告)日：2023-01-31

申请号：US17222024

申请日：2021-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Jinwoo Park ,  Hyunjun Yoon ,  Yoonhee Choi

IPC: G11C16/06 ,  G11C7/06 ,  G11C7/10 ,  G11C16/34

Abstract: A memory device includes a memory cell array, a page buffer circuit, and a counting circuit. The page buffer circuit includes a first and second page buffer columns connected to the memory cell array. The first page buffer column includes a first page buffer unit and the second page buffer column includes a second page buffer unit in a first stage. The first page buffer unit performs a first sensing operation in response to a first sensing signal, and the second page buffer unit performs a second sensing operation in response to a second sensing signal. The counting circuit counts a first number of memory cells included in a first threshold voltage region from a result of the first sensing operation, and counts a second number of memory cells included in a second threshold voltage region from a result of the second sensing operation.

公开(公告)号：US20220187366A1

公开(公告)日：2022-06-16

申请号：US17465337

申请日：2021-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heejune Lee ,  Jinwoo Park ,  Younghyo Park ,  Eunhye Oh ,  Sungno Lee ,  Youngjae Cho ,  Michael Choi

IPC: G01R31/317 ,  H03M1/10

Abstract: A semiconductor integrated circuit includes a digital-to-analog converter and a built-in self-test circuit. The digital-to-analog converter performs a normal conversion operation to generate an analog output signal by converting a digital input signal corresponding to an external digital signal that is provided from an external device outside the semiconductor integrated circuit and provide the analog output signal to the external device. The built-in self-test circuit, while the digital-to-analog converter performs the normal conversion operation, performs a real-time monitoring operation to generate a comparison alarm signal based on the digital input signal and the analog output signal such that the comparison alarm signal indicates whether the digital-to-analog converter operates normally. Performance and reliability of the digital-to-analog converter and the semiconductor integrated circuit including the digital-to-analog converter may be enhanced by monitoring in real-time abnormality of the digital-to-analog converter using the on-time monitor.

公开(公告)号：US10790866B2

公开(公告)日：2020-09-29

申请号：US16705795

申请日：2019-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungsik Park ,  Yoonjung Kim ,  Gyubok Park ,  Dongyeon Kim ,  Yonghwa Kim ,  Jinwoo Park ,  Jinho Lim

IPC: H04M1/00 ,  H04B1/3827 ,  H01Q9/04 ,  H01Q9/16 ,  H01Q5/307 ,  H04R1/02 ,  H01Q1/48

Abstract: An electronic device is provided. The electronic device includes a front plate disposed on a display, a back plate disposed on a back surface of the electronic device, a side member placed between the front plate and the back plate and forming an outer appearance of the electronic device together with the front plate and the back plate, and first, second, and third antenna modules including a plurality of conductive plates configured to transmit/receive a signal in a specified first frequency band and disposed between the front plate and the back plate so as to be adjacent to the side member. At least a portion of the side member is able to be used as an antenna of a signal in a specified second frequency band different from the specified first frequency band.

公开(公告)号：US10237651B2

公开(公告)日：2019-03-19

申请号：US15235639

申请日：2016-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beakkwon Son ,  Gangyoul Kim ,  Yangsu Kim ,  Chulmin Choi ,  Jinwoo Park ,  Gunhyuk Yoon ,  Namil Lee ,  Yonghoon Lee ,  Keunwon Jang ,  Seungyoon Heo

IPC: H03G3/20 ,  H04R3/04 ,  H04R29/00 ,  G10L19/16 ,  H03G3/32 ,  H03G3/30 ,  H03G5/16 ,  H03G7/00

Abstract: An audio processing method and an electronic device for supporting the same are provided. The audio signal processing method includes checking property information of an audio signal in response to a request for playing the audio signal; processing, when property information fulfills a first condition, the audio signal using the first method and, when the property information fulfills a second condition, the audio signal using the second method; and outputting the audio signal processed using one of the first and second methods through a speaker.