公开(公告)号：US06351013B1

公开(公告)日：2002-02-26

申请号：US09352339

申请日：1999-07-13

Applicant: Scott Luning ,  David Wu ,  Khanh Tran

Inventor： Scott Luning ,  David Wu ,  Khanh Tran

IPC: H01L31062

CPC classification number: H01L29/6659 ,  H01L21/02134 ,  H01L21/02282 ,  H01L21/3124 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/66598 ,  Y10S257/90

Abstract: The capacitance between the gate electrode and the source/drain regions of a semiconductor device is reduced by forming sub-spacers of a low dielectric constant (K) material at the corners of the gate electrode above the source/drain regions. Subsequently, insulating sidewall spacers are formed over the sub-spacers to shield-shallow source/drain regions from subsequent impurity implantations. The resulting semiconductor device exhibits reduced capacitance between the gate electrode and the source/drain regions, while maintaining circuit reliability.

Abstract translation: 通过在源极/漏极区域之上的栅电极的角部形成低介电常数（K）材料的子间隔物来减小半导体器件的栅电极和源/漏区之间的电容。 随后，在子间隔物之上形成绝缘侧壁间隔物以屏蔽浅源/漏区，从而避免随后的杂质注入。 所得到的半导体器件在保持电路可靠性的同时，在栅极电极和源极/漏极区域之间表现出减小的电容。

公开(公告)号：US6114210A

公开(公告)日：2000-09-05

申请号：US979364

申请日：1997-11-26

Applicant: David Wu ,  Scott Luning

Inventor： David Wu ,  Scott Luning

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/26586 ,  H01L29/66659 ,  H01L29/7835

Abstract: A CMOS semiconductor device is formed having an N-channel transistor comprising a drain region with a graded N-LDD junction. The graded N-LDD junction is obtained by plural ion implantations at different implantation dosages, energies and angles. The graded N-LDD junction reduces the electric field around the drain, thereby increasing the HCI lifetime without adversely impacting the short channel effect.

Abstract translation: 形成具有N沟道晶体管的CMOS半导体器件，N沟道晶体管包括具有渐变N-LDD结的漏极区。 通过以不同植入剂量，能量和角度的多个离子注入获得分级N-LDD结。 分级N-LDD结降低了漏极周围的电场，从而提高了HCl寿命，而不会对短沟道效应产生不利影响。

公开(公告)号：US5952693A

公开(公告)日：1999-09-14

申请号：US923996

申请日：1997-09-05

Applicant: David Wu ,  Scott Luning

Inventor： David Wu ,  Scott Luning

IPC: H01L21/265 ,  H01L21/336 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L27/092 ,  H01L29/6656 ,  H01L29/7833 ,  H01L21/2652 ,  Y10S257/917

Abstract: A CMOS semiconductor device is formed having an N-channel transistor comprising a graded junction with reduced junction capacitance. The graded junction is achieved by forming a second sidewall spacer on the gate electrode, after source/drain implantations, and ion-implanting an N-type impurity with high diffusivity, e.g., P into an A.sub.5 implant, followed by activation annealing.

公开(公告)号：US5646448A

公开(公告)日：1997-07-08

申请号：US699821

申请日：1996-08-19

Applicant: Richard K. Klein ,  Darrell Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

Inventor： Richard K. Klein ,  Darrell Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76805 ,  H01L21/76877 ,  Y10S257/915 ,  Y10S438/927

Abstract: A multilayer semiconductor structure includes a conductive via. The conductive via includes a pellet of metal having a high resistance to electromigration. The pellet is made from a conformal layer of copper or gold deposited over the via to form a copper or gold reservoir or contact located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the pellet from diffusing into the insulating layer. The pellet can be formed by selective deposition or by etching a conformal layer. The conformal layer can be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and pellet may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.

Abstract translation: 多层半导体结构包括导电通孔。 导电通孔包括具有高抗电迁移性的金属颗粒。 沉淀物由沉积在通孔上的铜或金的保形层制成，以形成位于通孔中的铜或金储存器或触点。 在储存器和绝缘层之间设置阻挡层以防止颗粒扩散到绝缘层中。 颗粒可以通过选择性沉积或通过蚀刻保形层形成。 可以通过溅射，准直溅射，化学气相沉积（CVD），浸渍，蒸发或其它方式沉积共形层。 可以通过各向异性干蚀刻，等离子体辅助蚀刻或其它层去除技术来蚀刻阻挡层和颗粒。