公开(公告)号：US09768318B2

公开(公告)日：2017-09-19

申请号：US15019004

申请日：2016-02-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Yoshinobu Asami ,  Yutaka Okazaki ,  Motomu Kurata ,  Katsuaki Tochibayashi ,  Shinya Sasagawa ,  Kensuke Yoshizumi ,  Hideomi Suzawa

IPC: H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/4757 ,  H01L21/47 ,  H01L21/477 ,  H01L33/00

CPC classification number: H01L29/7869 ,  H01L21/47 ,  H01L21/4757 ,  H01L21/477 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/66969 ,  H01L29/78648 ,  H01L33/00

Abstract: A miniaturized transistor, a transistor with low parasitic capacitance, a transistor with high frequency characteristics, or a semiconductor device including the transistor is provided. The semiconductor device includes a first insulator, an oxide semiconductor over the first insulator, a first conductor and a second conductor that are in contact with the oxide semiconductor, a second insulator that is over the first and second conductors and has an opening reaching the oxide semiconductor, a third insulator over the oxide semiconductor and the second insulator, and a fourth conductor over the third insulator. The first conductor includes a first region and a second region. The second conductor includes a third region and a fourth region. The second region faces the third region with the first conductor and the first insulator interposed therebetween. The second region is thinner than the first region. The third region is thinner than the fourth region.

公开(公告)号：US09685500B2

公开(公告)日：2017-06-20

申请号：US14645566

申请日：2015-03-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Yutaka Shionoiri ,  Tomoaki Atsumi ,  Shuhei Nagatsuka ,  Yutaka Okazaki ,  Suguru Hondo

IPC: H01L29/12 ,  H01L29/04 ,  H01L27/12 ,  H01L29/786 ,  H01L29/24 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/06

CPC classification number: H01L29/045 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device with a transistor having favorable electrical characteristics is provided. The semiconductor device has a memory circuit and a circuit that are over the same substrate. The memory circuit includes a capacitor, a first transistor, and a second transistor. A gate of the first transistor is electrically connected to the capacitor and one of a source and a drain of the second transistor. The circuit includes a third transistor and a fourth transistor that are electrically connected to each other in series. The first transistor and the third transistor each include an active layer including silicon, and the second transistor and the fourth transistor each include an active layer including an oxide semiconductor.

公开(公告)号：US09660100B2

公开(公告)日：2017-05-23

申请号：US15011833

申请日：2016-02-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka Okazaki

IPC: H01L21/3205 ,  H01L21/44 ,  H01L21/4763 ,  H01L23/52 ,  H01L29/786 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L29/7869 ,  H01L21/76805 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78696 ,  H01L2221/1031

Abstract: A semiconductor device is formed in such a manner that a first insulator, a first oxide semiconductor, and a first conductor are formed; the first conductor is processed to form a second conductor; the first oxide semiconductor is processed to form a second oxide semiconductor; a second insulator is formed over the second conductor; a third insulator is formed over the second insulator; a fourth insulator is formed over the third insulator; the fourth insulator, the third insulator, the second insulator, and the second conductor are selectively processed to partly expose the second oxide semiconductor; a fifth insulator is formed over the second oxide semiconductor and the fourth insulator; and a third conductor is formed over the fifth insulator and then chemical mechanical polishing treatment is performed to expose a top surface of the fourth insulator.

公开(公告)号：US20170040457A1

公开(公告)日：2017-02-09

申请号：US15224958

申请日：2016-08-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka Okazaki ,  Daisuke MATSUBAYASHI ,  Yuichi SATO

IPC: H01L29/786 ,  H01L29/45 ,  H01L21/441 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/441 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7853 ,  H01L29/78603 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A semiconductor device in which parasitic capacitance is reduced is provided. A first insulating layer is deposited over a substrate. A first oxide insulating layer and an oxide semiconductor layer are deposited over the first insulating layer. A second oxide insulating layer is deposited over the oxide semiconductor layer and the first insulating layer. A second insulating layer and a first conductive layer are deposited over the second oxide insulating layer. A gate electrode layer, a gate insulating layer, and a third oxide insulating layer are formed by etching. A sidewall insulating layer including a region in contact with a side surface of the gate electrode layer is formed. A second conductive layer is deposited over the gate electrode layer, the sidewall insulating layer, the oxide semiconductor layer, and the first insulating layer. A third conductive layer is deposited over the second conductive layer. A low-resistance region is formed in the oxide semiconductor layer by performing heat treatment. An element contained in the second conductive layer moves from the second conductive layer to the oxide semiconductor layer side by performing the heat treatment. An element contained in the oxide semiconductor layer moves from the oxide semiconductor layer to the third conductive layer side by performing the heat treatment.

Abstract translation: 提供其中寄生电容减小的半导体器件。 第一绝缘层沉积在衬底上。 在第一绝缘层上沉积第一氧化物绝缘层和氧化物半导体层。 第二氧化物绝缘层沉积在氧化物半导体层和第一绝缘层上。 在第二氧化物绝缘层上沉积第二绝缘层和第一导电层。 通过蚀刻形成栅极电极层，栅极绝缘层和第三氧化物绝缘层。 形成包括与栅电极层的侧面接触的区域的侧壁绝缘层。 在栅电极层，侧壁绝缘层，氧化物半导体层和第一绝缘层上沉积第二导电层。 在第二导电层上沉积第三导电层。 通过进行热处理，在氧化物半导体层中形成低电阻区域。 包含在第二导电层中的元素通过进行热处理从第二导电层移动到氧化物半导体层侧。 包含在氧化物半导体层中的元素通过进行热处理从氧化物半导体层移动到第三导电层侧。