公开(公告)号：US20110310687A1

公开(公告)日：2011-12-22

申请号：US12820050

申请日：2010-06-21

Applicant: ONEGYUN NA ,  Jongtae Kwak ,  Seong-Hoon Lee ,  Hoon Choi

Inventor： ONEGYUN NA ,  Jongtae Kwak ,  Seong-Hoon Lee ,  Hoon Choi

IPC: G11C7/06 ,  H03F3/45

CPC classification number: G11C11/4091 ,  G11C7/02 ,  G11C7/06 ,  G11C7/062 ,  G11C7/065 ,  G11C11/4074 ,  G11C2207/063 ,  G11C2207/2281

Abstract: A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals.

Abstract translation: 电流检测放大器可以包括耦合在放大器的差分输出节点之间的一个或多个钳位电路。 钳位电路可以在读出放大器感测耦合到读出放大器的差分输入的存储器单元的状态的至少一部分期间被使能。 在读出放大器以不同的时间以交错的方式感测存储器单元的状态的时间期间，钳位电路可能被禁用。 钳位电路可能正在使电流检测放大器对噪声信号较不敏感。

公开(公告)号：US20110254627A1

公开(公告)日：2011-10-20

申请号：US12760922

申请日：2010-04-15

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: H03F3/04 ,  H03F1/00

CPC classification number: H03F3/245 ,  H03K19/00315 ,  H04L25/0272

Abstract: Signaling systems, preamplifiers, memory devices and methods are disclosed, such as a signaling system that includes a transmitter configured to receive a first digital signal. The transmitter provides a transmitted signal corresponding to the digital signal to a signal path. A receiver system coupled to the signal line includes a preamplifier coupled to receive the transmitted signal from the signal path. The preamplifier includes a common-gate amplifying transistor that is configured to provide an amplified signal. The receiver system also includes a receiver coupled to receive the amplified signal from the preamplifier. The receiver is configured to provide a second digital signal corresponding to the amplified signal received by the receiver. Such a signaling system may be used in a memory device or in any other electronic circuit.

Abstract translation: 公开了信号系统，前置放大器，存储器件和方法，例如包括被配置为接收第一数字信号的发射器的信令系统。 发射机将对应于数字信号的发射信号提供给信号路径。 耦合到信号线的接收机系统包括前置放大器，其被耦合以从信号路径接收发送的信号。 前置放大器包括配置成提供放大信号的共栅放大晶体管。 接收机系统还包括接收器，用于从前置放大器接收放大的信号。 接收器被配置为提供对应于由接收器接收的放大信号的第二数字信号。 这样的信令系统可以用在存储器装置或任何其它电子电路中。

公开(公告)号：US20110182129A1

公开(公告)日：2011-07-28

申请号：US12694136

申请日：2010-01-26

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: G11C7/08 ,  H03F3/04 ,  H03F3/45

CPC classification number: G11C7/065 ,  G11C7/062 ,  G11C7/08 ,  G11C7/12 ,  H03F3/45179 ,  H03G3/00

Abstract: Memories, sense amplifiers, and methods for amplifying a current input are disclosed, including a sense amplifier including a bias circuit configured to provide a bias voltage having a magnitude responsive to maintaining a substantially constant loop gain, and further including an amplifier stage coupled to the bias circuit to receive the bias voltage and configured to amplify a input current at an input-output node, a loop gain of the current amplifier stage is controlled at least in part to the bias voltage.

Abstract translation: 公开了用于放大电流输入的存储器，感测放大器和放大电流输入的方法，包括读出放大器，其包括偏置电路，该偏置电路被配置为提供具有响应于保持基本上恒定的环路增益的幅度的偏置电压，并且还包括耦合到 偏置电路以接收所述偏置电压并且被配置为放大输入 - 输出节点处的输入电流，所述电流放大器级的环路增益至少部分地被控制为所述偏置电压。

公开(公告)号：US20110007591A1

公开(公告)日：2011-01-13

申请号：US12500207

申请日：2009-07-09

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: G11C7/00 ,  H03M9/00 ,  G11C8/18

CPC classification number: G11C7/1051 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1072 ,  G11C11/4093 ,  G11C2207/107 ,  H03M9/00

Abstract: Data serializers, output buffers, memory devices and methods for serializing are provided, including a data serializer that may convert digits of parallel data to a stream of corresponding digits of serial data digits. One such data serializer may include a logic system receiving the parallel data digits and clock signals having phases that are equally phased apart from each other. Such a data serializer may use the clock signals to generate data sample signals having a value corresponding to the value of a respective one of the parallel data digits and a timing corresponding to a respective one of the clock signals. The data sample signals may be applied to a switching circuit that includes a plurality of switches, such as respective transistors, coupled to each other in parallel between an output node and a first voltage. A bias element may bias the output node to a second voltage. Each of the switches may be controlled by a respective one of the sample signals.

Abstract translation: 提供了数据串行器，输出缓冲器，存储器件和用于串行化的方法，包括可将并行数据的数字转换为串行数据数字的对应数字流的数据串行器。 一个这样的数据串行器可以包括接收并行数据位的逻辑系统和具有彼此相位分开的相位的时钟信号。 这样的数据串行器可以使用时钟信号来生成具有对应于并行数据位中的相应一个的值的值的数据采样信号和对应于相应的一个时钟信号的定时。 数据采样信号可以被施加到包括在输出节点和第一电压之间并联耦合的多个开关（诸如相应的晶体管）的开关电路。 偏置元件可将输出节点偏置到第二电压。 每个开关可以由相应的一个采样信号来控制。

公开(公告)号：US20100060320A1

公开(公告)日：2010-03-11

申请号：US12209051

申请日：2008-09-11

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: H03K19/0185 ,  G11C7/10

CPC classification number: G11C7/1051 ,  G11C7/1057 ,  G11C8/06 ,  G11C8/08 ,  H03K19/018521

Abstract: Processor-based systems, memories, signal driver circuits, and methods of generating an output signal are disclosed. One such signal driver circuit includes a signal driver configured to generate an output signal at an output node in response to an input signal and a transistor coupled to the signal driver that is configured to couple and decouple the output node and the voltage supply according to a control signal. A voltage comparator circuit coupled to the output node and the transistor is configured to generate the control signal to control coupling and decoupling of the output node and the voltage supply through the transistor based on a voltage of the output signal relative to the reference voltage.

Abstract translation: 公开了基于处理器的系统，存储器，信号驱动器电路和产生输出信号的方法。 一个这样的信号驱动器电路包括信号驱动器，其被配置为响应于输入信号在输出节点处产生输出信号，以及耦合到信号驱动器的晶体管，其被配置为根据输出信号耦合和去耦输出节点和电压源 控制信号。 耦合到输出节点和晶体管的电压比较器电路被配置为产生控制信号，以基于输出信号相对于参考电压的电压来控制输出节点和通过晶体管的电压源的耦合和去耦。

公开(公告)号：US20090256592A1

公开(公告)日：2009-10-15

申请号：US12101770

申请日：2008-04-11

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: H03K19/094 ,  H03K19/0175

CPC classification number: G11C5/147 ,  H02M3/1563 ,  H03K17/687 ,  H03K19/018507 ,  H03K19/018585

Abstract: A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured to output a first logic level signal having a first voltage and output a second logic level signal having a second voltage according to an input signal. A voltage controlled voltage supply coupled to the signal driver provides the first voltage for the first logic level signal. The magnitude of the first voltage provided by the voltage controlled voltage supply is based on a bias voltage. A bias voltage generator can be coupled to the voltage controlled voltage supply to provide the bias voltage.

Abstract translation: 具有用于高逻辑电平输出信号的可调输出电压的信号驱动器电路。 信号驱动器电路包括：信号驱动器，被配置为输出具有第一电压的第一逻辑电平信号，并输出具有根据输入信号的第二电压的第二逻辑电平信号。 耦合到信号驱动器的电压控制电压电源为第一逻辑电平信号提供第一电压。 由压控电压提供的第一电压的大小基于偏置电压。 偏置电压发生器可以耦合到压控电压源以提供偏置电压。

公开(公告)号：US20080309377A1

公开(公告)日：2008-12-18

申请号：US11762557

申请日：2007-06-13

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: H03D13/00

CPC classification number: H03D13/004

Abstract: Methods and apparatus are disclosed, such as those involving a digital phase detector that includes a phase detection circuit configured to detect which one of two clock signals leads the other. One such phase detector includes a balancer configured to prepare the phase detection circuit for a phase detection. The phase detection circuit of one or more embodiments includes a cross-coupled latch configured to receive the two clock signals and generate a first latch output and a second latch output in response to the two clock signals. The aforementioned balancer is configured to substantially equalize the voltage levels of the first and second latch outputs before the phase detection circuit detects a phase difference between the two clock signals. For example, the balancer might pre-charge the outputs of the phase detection circuit to substantially the same voltage level before phase detection.

Abstract translation: 公开了诸如涉及数字相位检测器的方法和装置，该数字相位检测器包括被配置为检测两个时钟信号中的哪一个引导另一个的相位检测电路。 一个这样的相位检测器包括配置成准备用于相位检测的相位检测电路的平衡器。 一个或多个实施例的相位检测电路包括交叉耦合锁存器，其被配置为接收两个时钟信号，并响应于两个时钟信号产生第一锁存器输出和第二锁存器输出。 上述平衡器被配置为在相位检测电路检测到两个时钟信号之间的相位差之前基本均衡第一和第二锁存器输出的电压电平。 例如，平衡器可以在相位检测之前将相位检测电路的输出预充电至基本相同的电压电平。

公开(公告)号：US07372310B2

公开(公告)日：2008-05-13

申请号：US11195154

申请日：2005-08-01

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: H03L7/06

CPC classification number: H03L7/18 ,  H03L7/089 ,  H03L7/0997 ,  H03L7/0998

Abstract: Digital delay-locked loops (DLLs) and methods are provided for signal frequency multiplication. Analog delay elements of typical frequency-multiplying DLLs are replaced with digital and digitally-controlled elements including a variable delay line. The number of unit delay elements in the delay line can be selected to produce a desired output signal delay. Phase-mixing of multiple variable delay line outputs achieves finer delay-time adjustments.

Abstract translation: 数字延迟锁定环（DLL）和方法用于信号倍频。 典型倍频DLL的模拟延迟元件由包括可变延迟线的数字和数字控制元件代替。 可以选择延迟线中的单位延迟元件的数量以产生期望的输出信号延迟。 多个可变延迟线输出的相位混合实现更精细的延迟时间调整。

公开(公告)号：US07355464B2

公开(公告)日：2008-04-08

申请号：US11124743

申请日：2005-05-09

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/10

Abstract: A method and circuitry for a Delay Locked Loop (DLL) or a phase Locked Loop (PLL) is disclosed, which improves the loop stability at high frequencies and allows maximum tracking bandwidth, regardless of process, voltage, or temperature variations. Central to the technique is to effectively operate the loop at a lower frequency close to its own intrinsic bandwidth (1/tLoop) instead of at the higher frequency of the clock signal (1/tCK). To do so, in one embodiment, the loop delay, tLoop, is measured or estimated prior to operation of the loop. The phase detector is then enabled to operate close to the loop frequency, 1/tLoop. In short, the phase detector is made not to see activity during useless delay times, which prevents the loop from overreacting and becoming unstable.

Abstract translation: 公开了用于延迟锁定环（DLL）或锁相环（PLL）的方法和电路，其改善了高频下的环路稳定性，并允许最大跟踪带宽，而不管过程，电压或温度变化。 该技术的核心是以更接近其自身固有带宽（1 / tLoop）的较低频率有效地操作环路，而不是在时钟信号（1 / tCK）的较高频率处。 为了做到这一点，在一个实施例中，在循环操作之前测量或估计环路延迟t L oop。 然后，相位检测器使能接近环路频率1 / tLoop。 简而言之，使相位检测器在无用的延迟时间期间看不到活动，从而防止环路过度反应并变得不稳定。

公开(公告)号：US07336548B2

公开(公告)日：2008-02-26

申请号：US11542918

申请日：2006-10-03

Applicant: Seong-Hoon Lee

Inventor： Seong-Hoon Lee

IPC: G11C7/00

CPC classification number: G11C7/1072 ,  G11C7/222 ,  H03L7/0812 ,  H03L7/095 ,  H03L7/0995

Abstract: A clock generating circuit includes a phase comparison circuit that generates a delay control signal corresponding to the relative phases of an output clock signal and a reference clock signal. A voltage controlled delay circuit generates the delayed clock signal by inverting a signal applied to its input and delaying the signal by a delay that is determined by a delay control signal. A selection circuit couples either the reference clock signal or the delayed clock signal to the input of the voltage controlled delay circuit. When the reference clock signal is coupled to the input of the voltage controlled delay circuit, the clock generating circuit functions as a delay-lock loop. When the delayed clock signal is coupled to the input of the voltage controlled delay circuit, the voltage controlled delay circuit operates as a ring oscillator so that the clock generating circuit functions as a phase-lock loop.

Abstract translation: 时钟发生电路包括相位比较电路，其产生对应于输出时钟信号和参考时钟信号的相对相位的延迟控制信号。 电压控制延迟电路通过反相施加到其输入的信号并延迟由延迟控制信号确定的延迟来产生延迟的时钟信号。 选择电路将参考时钟信号或延迟时钟信号耦合到电压控制延迟电路的输入端。 当参考时钟信号耦合到电压控制延迟电路的输入时，时钟发生电路用作延迟锁定环路。 当延迟时钟信号耦合到电压控制延迟电路的输入端时，电压控制延迟电路作为环形振荡器工作，使得时钟发生电路用作锁相环。