公开(公告)号：US08258619B2

公开(公告)日：2012-09-04

申请号：US12617169

申请日：2009-11-12

申请人： Jimmy G. Foster, Sr. ,  Kyu-Hyoun Kim

发明人： Jimmy G. Foster, Sr. ,  Kyu-Hyoun Kim

IPC分类号： H01L23/04

CPC分类号： H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/19051

摘要： An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, shifted in position with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are translationally compatible with respect to the TSVs and PTVs on the other identical die.

摘要翻译： 一种集成电路管芯堆叠，其包括安装在衬底上的第一集成电路管芯，所述第一管芯包括由通过所述第一管芯的导电通路组成的通孔（“PTV”），其没有连接到所述第一管芯上的任何电路; 以及与第一裸片相同的第二集成电路裸片相对于第一裸片位置偏移并安装在第一裸片上，第一裸片中的PTV将来自衬底的信号线通过第一裸片连接至硅通孔 （“TSV”），其由通过第二管芯的导电通路组成，连接到第二管芯上的电子电路; 其中TSV和PTV设置在每个相同的管芯上，使得每个相同管芯上的TSV和PTV的位置相对于另一个相同管芯上的TSV和PTV平移兼容。

公开(公告)号：US20120218024A1

公开(公告)日：2012-08-30

申请号：US13462994

申请日：2012-05-03

申请人： Jimmy G. Foster, SR. ,  Kyu-Hyoun Kim

发明人： Jimmy G. Foster, SR. ,  Kyu-Hyoun Kim

IPC分类号： H03K17/00 ,  H01L21/50 ,  G06F1/10 ,  H01L23/498

CPC分类号： H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/19051

摘要： An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, shifted in position with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are translationally compatible with respect to the TSVs and PTVs on the other identical die.

摘要翻译： 一种集成电路管芯堆叠，其包括安装在衬底上的第一集成电路管芯，所述第一管芯包括由通过所述第一管芯的导电通路组成的通孔（“PTV”），其没有连接到所述第一管芯上的任何电路; 以及与第一裸片相同的第二集成电路裸片相对于第一裸片位置偏移并安装在第一裸片上，第一裸片中的PTV将来自衬底的信号线通过第一裸片连接到硅通孔 （“TSV”），其由通过第二管芯的导电通路组成，连接到第二管芯上的电子电路; 其中TSV和PTV设置在每个相同的管芯上，使得每个相同管芯上的TSV和PTV的位置相对于另一个相同管芯上的TSV和PTV平移兼容。

公开(公告)号：US20120020171A1

公开(公告)日：2012-01-26

申请号：US12840879

申请日：2010-07-21

申请人： Kevin C. Gower ,  Lisa C. Gower ,  Kyu-Hyoun Kim ,  Warren E. Maule

发明人： Kevin C. Gower ,  Lisa C. Gower ,  Kyu-Hyoun Kim ,  Warren E. Maule

IPC分类号： G11C8/18 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C2207/2227

摘要： A memory system with delay locked loop (DLL) bypass control including a method for accessing memory that includes receiving a memory read command at a memory device. The memory device is configured to operate in a DLL off-mode to bypass a DLL clock as input to generating a read clock. A DLL power-on command is received at the memory device and in response to receiving the DLL power-on command a DLL initialization process is performed at the memory device. The memory read command is serviced at the memory device operating in the DLL off-mode, the servicing overlapping in time with performing the DLL initialization process. The memory device is configured to operate in a DLL on-mode to utilize the DLL clock as input to generating the read clock in response to a specified period of time elapsing. The specified period of time is relative to receiving the DLL power-on command.

摘要翻译： 具有延迟锁定环（DLL）旁路控制的存储器系统，包括用于访问存储器的方法，包括在存储器件处接收存储器读命令。 存储器件被配置为以DLL关闭模式操作以绕过DLL时钟作为生成读取时钟的输入。 在存储器装置处接收到DLL加电命令，并且响应于接收到DLL加电命令，在存储器件执行DLL初始化处理。 存储器读取命令在以DLL关闭模式操作的存储器件处被服务，在执行DLL初始化过程时，服务与时间重叠。 存储器装置被配置为以模拟DLL操作以利用DLL时钟作为输入，以响应于经过指定的时间段来生成读取时钟。 指定的时间段相对于接收DLL上电命令。

公开(公告)号：US20110110064A1

公开(公告)日：2011-05-12

申请号：US12616912

申请日：2009-11-12

申请人： Jimmy G. Foster, SR. ,  Kyu-Hyoun Kim

发明人： Jimmy G. Foster, SR. ,  Kyu-Hyoun Kim

IPC分类号： H05K1/11 ,  H01L25/11 ,  H01L23/538 ,  H01L21/50 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L23/5256 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by blowing fuses on the first die, converting the TSVs previously connected through the blown fuses into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by blowing fuses on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.

摘要翻译： 具有安装在基板上的第一管芯的集成电路管芯堆叠，所述第一管芯被制造成与具有多个穿通硅通孔（“TSV”）的第二管芯初始相同，所述第一管芯通过在第一管芯上吹入保险丝来个性化， 将先前通过熔断保险丝连接的TSV转换成通过通孔（“PTV”），每个PTV通过第一管芯实现导电通路，而不连接到第一管芯上的任何电路; 以及第二模具，其被制造为与第一模具初始相同，然后通过在第二模具上吹入熔丝而进行个性化，第二模具安装在第一模具上，使得第一模具中的PTV将来自基板的信号线连接到第一模具 在第二次死亡时死于TSV。

公开(公告)号：US20110108972A1

公开(公告)日：2011-05-12

申请号：US12617169

申请日：2009-11-12

申请人： Jimmy G. Foster, SR. ,  Kyu-Hyoun Kim

发明人： Jimmy G. Foster, SR. ,  Kyu-Hyoun Kim

IPC分类号： H01L25/065 ,  H01L21/77

CPC分类号： H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/19051

摘要： An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, shifted in position with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are translationally compatible with respect to the TSVs and PTVs on the other identical die.

摘要翻译： 一种集成电路管芯堆叠，其包括安装在衬底上的第一集成电路管芯，所述第一管芯包括由通过所述第一管芯的导电通路组成的通孔（“PTV”），其没有连接到所述第一管芯上的任何电路; 以及与第一裸片相同的第二集成电路裸片相对于第一裸片位置偏移并安装在第一裸片上，第一裸片中的PTV将来自衬底的信号线通过第一裸片连接到硅通孔 （“TSV”），其由通过第二管芯的导电通路组成，连接到第二管芯上的电子电路; 其中TSV和PTV设置在每个相同的管芯上，使得每个相同管芯上的TSV和PTV的位置相对于另一个相同管芯上的TSV和PTV平移兼容。

公开(公告)号：US07778042B2

公开(公告)日：2010-08-17

申请号：US12143126

申请日：2008-06-20

申请人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

发明人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

IPC分类号： H05K1/11

CPC分类号： G11C5/063

摘要： A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.

摘要翻译： 存储器系统具有第一和第二主存储器以及分别耦合到第一和第二主存储器的第一和第二辅助存储器，耦合器包括至少一个点到点连接。 存储器模块包括第一和第二主要和第一和第二辅助存储器中的至少两个。 诸如连接器或焊料的第一连接元件将存储器模块连接到母板。 诸如连接器或焊料的第二连接元件将第一和第二初级和第二和第二辅助存储器中的至少一个连接到母板。 第一存储器模块上的至少一个存储器耦合到至少一个其他存储器。 存储器系统还包括存储器控制器，其通过点对二点链接连接到主存储器。

公开(公告)号：US20090085650A1

公开(公告)日：2009-04-02

申请号：US12325846

申请日：2008-12-01

申请人： Jin-Kyoung Jung ,  Jung-Bae Lee ,  Kyu-Hyoun Kim

发明人： Jin-Kyoung Jung ,  Jung-Bae Lee ,  Kyu-Hyoun Kim

IPC分类号： G05F3/02

CPC分类号： G05F1/465

摘要： An internal voltage generating circuit is provided. The internal voltage generating circuit of a semiconductor device includes a control signal generating circuit for generating a control signal according to a number of data bits, a comparator for comparing a reference voltage to an internal voltage to generate a driving signal when the control signal is inactivated, a driving signal control circuit for inactivating the driving signal when the control signal is activated, and an internal voltage driving circuit for receiving an external power voltage and generating the internal voltage in response to the driving signal. Therefore, an internal voltage can be turned to a reference voltage level or to an external power voltage level according to the number of data input and/or output bits of a semiconductor device, and even when the number of data input and/or output bits is increased, a data access speed can be improved.

摘要翻译： 提供内部电压产生电路。 半导体器件的内部电压产生电路包括：控制信号发生电路，用于根据多个数据位产生控制信号;比较器，用于将参考电压与内部电压进行比较，以在控制信号失效时产生驱动信号 ，用于当所述控制信号被激活时使所述驱动信号失活的驱动信号控制电路和用于接收外部电源电压并且响应于所述驱动信号产生所述内部电压的内部电压驱动电路。 因此，可以根据半导体器件的数据输入和/或输出位的数量将内部电压转换为参考电压电平或外部电源电压，并且即使当数据输入和/或输出位数 增加，可以提高数据访问速度。

公开(公告)号：US20080247212A1

公开(公告)日：2008-10-09

申请号：US12143126

申请日：2008-06-20

申请人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

发明人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

IPC分类号： G11C5/06

CPC分类号： G11C5/063

摘要： A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.

摘要翻译： 存储器系统具有第一和第二主存储器以及分别耦合到第一和第二主存储器的第一和第二辅助存储器，耦合器包括至少一个点到点连接。 存储器模块包括第一和第二主要和第一和第二辅助存储器中的至少两个。 诸如连接器或焊料的第一连接元件将存储器模块连接到母板。 诸如连接器或焊料的第二连接元件将第一和第二初级和第二和第二辅助存储器中的至少一个连接到母板。 第一存储器模块上的至少一个存储器耦合到至少一个其他存储器。 存储器系统还包括存储器控制器，其通过点对二点链接连接到主存储器。

公开(公告)号：US07405949B2

公开(公告)日：2008-07-29

申请号：US11603648

申请日：2006-11-22

申请人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

发明人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

IPC分类号： H05K7/14

CPC分类号： G11C5/063

摘要： A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.

摘要翻译： 存储器系统具有第一和第二主存储器以及分别耦合到第一和第二主存储器的第一和第二辅助存储器，耦合器包括至少一个点到点连接。 存储器模块包括第一和第二主要和第一和第二辅助存储器中的至少两个。 诸如连接器或焊料的第一连接元件将存储器模块连接到母板。 诸如连接器或焊料的第二连接元件将第一和第二初级和第二和第二辅助存储器中的至少一个连接到母板。 第一存储器模块上的至少一个存储器耦合到至少一个其他存储器。 存储器系统还包括存储器控制器，其通过点对二点链接连接到主存储器。

公开(公告)号：US07375564B2

公开(公告)日：2008-05-20

申请号：US10716146

申请日：2003-11-18

申请人： Geun-Hee Cho ,  Byung-Hoon Jeong ,  Kyu-Hyoun Kim

发明人： Geun-Hee Cho ,  Byung-Hoon Jeong ,  Kyu-Hyoun Kim

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03K5/135 ,  H03K2005/00208 ,  H03L7/0818

摘要： A delay-locked loop includes a phase detector, a delay line, and a filter unit. The phase detector compares the phase of the external clock signal with that of the feedback clock signal and outputs a phase difference as an error control signal. The delay line includes delay cells having various unit time delays. The number of delay cells is adjusted in response to a shift signal. The delay line receives the external clock signal and outputs an output clock signal. The filter unit generates the shift signal in response to the error control signal. In the delay-locked loop, the front delay cells, which compensate for a delay of an external clock signal having a high frequency, have short unit time delays. The rear delay cells, which compensate for a delay of the external clock signal having a low frequency, have long unit time delays.

摘要翻译： 延迟锁定环包括相位检测器，延迟线和滤波器单元。 相位检测器将外部时钟信号的相位与反馈时钟信号的相位进行比较，并输出相位差作为误差控制信号。 延迟线包括具有各种单位时间延迟的延迟单元。 响应于移位信号调整延迟单元的数量。 延迟线接收外部时钟信号并输出​​输出时钟信号。 滤波器单元响应于误差控制信号产生移位信号。 在延迟锁定环路中，补偿具有高频率的外部时钟信号的延迟的前延迟单元具有较短的单位时间延迟。 补偿具有低频率的外部时钟信号的延迟的后延迟单元具有长的单位时间延迟。