公开(公告)号：US20050251666A1

公开(公告)日：2005-11-10

申请号：US10923219

申请日：2004-08-20

申请人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

IPC分类号： G06F9/38 ,  G06F15/00

CPC分类号： G06F9/3842 ,  G06F9/30189 ,  G06F9/383 ,  G06F9/3838 ,  G06F9/3863

摘要： One embodiment of the present invention provides a system that avoids read-after-write (RAW) hazards while speculatively executing instructions on a processor. The system starts in a normal execution mode, wherein the system issues instructions for execution in program order. Upon encountering a stall condition during execution of an instruction, the system generates a checkpoint, and executes the instruction and subsequent instructions in a speculative-execution mode. The system also maintains dependency information for each register indicating whether or not a value in the register depends on an unresolved data-dependency. The system uses this dependency information to avoid RAW hazards during the speculative-execution mode.

摘要翻译： 本发明的一个实施例提供了一种在推测性地在处理器上执行指令时避免写后读取（RAW）危险的系统。 系统以正常执行模式启动，其中系统以程序顺序发出执行指令。 在执行指令期间遇到停顿状态时，系统生成检查点，并以推测执行模式执行指令和后续指令。 该系统还维护每个寄存器的依赖性信息，指示寄存器中的值是否取决于未解决的数据依赖性。 系统使用这种依赖信息来避免在推测执行模式下的RAW危害。

公开(公告)号：US06934809B2

公开(公告)日：2005-08-23

申请号：US10080859

申请日：2002-02-22

申请人： Marc Tremblay ,  Shailender Chaudhry

发明人： Marc Tremblay ,  Shailender Chaudhry

IPC分类号： G06F9/38 ,  G06F9/46 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F9/383 ,  G06F9/3455 ,  G06F12/0862 ,  G06F2212/6028

摘要： Techniques have been developed whereby likely pointer values are identified at runtime and contents of corresponding storage location can be prefetched into a cache hierarchy to reduce effective memory access latencies. In some realizations, one or more writable stores are defined in a processor architecture to delimit a portion or portions of a memory address space.

摘要翻译： 已经开发了技术，其中可能在运行时识别指针值，并且可以将对应的存储位置的内容预取到高速缓存层级以减少有效的存储器访问延迟。 在一些实现中，在处理器架构中定义一个或多个可写存储器以限定存储器地址空间的一部分或部分。

公开(公告)号：US20050081195A1

公开(公告)日：2005-04-14

申请号：US10686061

申请日：2003-10-14

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F9/00 ,  G06F9/38 ,  G06F9/45

CPC分类号： G06F9/3842 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865

摘要： One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order. During a normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint that can subsequently be used to return execution of the program to the point of the instruction. Next, the system executes subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order.

摘要翻译： 本发明的一个实施例提供了一种系统，其有助于在按照程序顺序执行时，推迟执行具有未解决的数据依赖性的指令。 在正常执行模式下，系统以程序顺序发出执行指令。 在执行指令期间遇到未解决的数据依赖性时，系统产生一个检查点，随后可以使用该检查点将程序的执行返回到指令点。 接下来，系统以执行模式执行后续指令，其中由于未解决的数据依赖性而不能执行的指令被延迟，并且其中其他非延迟指令以程序顺序执行。

公开(公告)号：US06772321B2

公开(公告)日：2004-08-03

申请号：US09761360

申请日：2001-01-16

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F1500

CPC分类号： G06F9/3877 ,  G06F9/383 ,  G06F9/3842

摘要： One embodiment of the present invention provides a system that prefetches from memory by using an assist processor that performs data speculation and that executes in advance of a primary processor. The system operates by executing executable code on the primary processor while simultaneously executing a reduced version of the executable code on the assist processor. This allows the assist processor to generate the same pattern of memory references that the primary processor generates in advance of when the primary processor generates the memory references. While executing the reduced version of the executable code, the system predicts a data value returned by a long latency operation within the executable code. The system subsequently uses the predicted data value to continue executing the reduced version of the executable code without having to wait for the long latency operation to complete.

摘要翻译： 本发明的一个实施例提供一种通过使用执行数据推测并且在主处理器之前执行的辅助处理器来从存储器预取的系统。 该系统通过在主处理器上执行可执行代码同时在辅助处理器上执行可执行代码的简化版本来操作。 这允许辅助处理器在主处理器产生存储器引用之前产生与主处理器产生的相同的存储器引用模式。 在执行可执行代码的缩减版本的同时，系统预测在可执行代码内的长延迟操作返回的数据值。 系统随后使用预测数据值继续执行可执行代码的简化版本，而不必等待长延迟操作完成。

公开(公告)号：US06463526B1

公开(公告)日：2002-10-08

申请号：US09420335

申请日：1999-10-18

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F952

CPC分类号： G06F9/3851 ,  G06F8/45 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3863 ,  G06F9/3885 ,  G06F12/084 ,  G06F2212/507

摘要： One embodiment of the present invention provides a system that facilitates multi-dimensional space and time dimensional execution of computer programs. The system includes a head thread that executes program instructions and a series of speculative threads that execute program instructions in advance of the head thread, wherein each speculative thread executes program instructions in advance of preceding speculative threads in the series. The head thread accesses a primary version of the memory element and the series of speculative threads access space-time dimensioned versions of the memory element. The system starts by receiving a memory access to the memory element. If the memory access is a write operation by the head thread or a speculative thread, the system determines if a version of the memory element associated with the head thread or speculative thread exists. If not, the system creates a version of the memory element for the thread. Next, the system performs the write operation to the version of the memory element. After performing the write operation, the system checks status information associated with the memory element to determine if the memory element has been read by a following speculative thread in the series of speculative threads. If so, the system causes the following speculative thread and any successive speculative threads in the series to roll back so that the following speculative thread and any successive speculative threads in the series can read a result of the write operation. If not, the system performs the write operation to all successive space-time dimensioned versions of the memory element.

摘要翻译： 本发明的一个实施例提供一种促进计算机程序的多维空间和时间尺寸执行的系统。 该系统包括执行程序指令的头螺纹和在头部线程之前执行程序指令的一系列推测线程，其中每个推测线程在该系列中的先前推测线程之前执行程序指令。 头线程访问存储器元件的主要版本，并且一系列推测线程访问存储器元件的时空维度版本。 系统通过接收存储器元件的存储器访问来开始。 如果存储器访问是头部线程或推测线程的写入操作，则系统确定是否存在与头部线程或推测线程相关联的存储器元件的版本。 如果没有，系统会创建线程的内存元素的版本。 接下来，系统对存储元件的版本执行写入操作。 在执行写入操作之后，系统检查与存储器元件相关联的状态信息，以确定存储器元件是否已被一系列推测性线程中的以下推测线程读取。 如果是这样，系统会导致以下推测线程和系列中任何连续的推测线程回滚，以便以下推测线程和系列中任何连续的推测线程可以读取写操作的结果。 如果没有，则系统对所有连续的时空维度版本的存储器元件执行写入操作。

公开(公告)号：US06460067B1

公开(公告)日：2002-10-01

申请号：US09327399

申请日：1999-06-07

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F1500

CPC分类号： G06F9/52

摘要： One embodiment provides for a system that uses a time stamp in order to more efficiently mark objects to keep track of accesses to fields with the objects. Upon receiving a first reference to a first field in an object, the system determines whether the first field has been accessed within a current time period. The system does so by retrieving a time stamp associated with the object. This time stamp indicates the last time any marking bit associated with any field in the object was updated. The system compares the time stamp with a current time value associated with the current time period. The system additionally retrieves a first marking bit associated with the first field and determines if the first marking bit is set. If the first marking bit is set and if the time stamp equals the current time value, the system determines that the first field has been accessed in the current time period. The system indicates that a second field in the object has been accessed in the current time period upon receiving a second reference to the second field. In response to the second reference, the system sets a second marking bit associated with the second field. The system also updates the time stamp associated with the object, if necessary, so that the time stamp contains the current time value.

摘要翻译： 一个实施例提供了一种使用时间戳的系统，以便更有效地标记对象以跟踪对具有对象的字段的访问。 在接收到对象中的第一个字段的第一个引用后，系统确定在当前时间段内是否已经访问了第一个字段。 系统通过检索与对象相关联的时间戳来实现。 该时间戳表示最后一次与对象中的任何字段相关联的任何标记位被更新。 系统将时间戳与当前时间段相关联的当前时间值进行比较。 系统还检索与第一场相关联的第一标记位，并确定是否设置了第一标记位。 如果设置了第一个标记位，并且如果时间戳等于当前时间值，则系统确定在当前时间段内已经访问了第一个字段。 系统指示当接收到对第二字段的第二个引用时，当前时间段中已经访问了该对象中的第二个字段。 响应于第二参考，系统设置与第二场相关联的第二标记位。 如果需要，系统还更新与对象相关联的时间戳，以便时间戳包含当前时间值。

公开(公告)号：US06438677B1

公开(公告)日：2002-08-20

申请号：US09422028

申请日：1999-10-20

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F952

CPC分类号： G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863

摘要： One embodiment of the present invention provides a system that supports space and time dimensional program execution by facilitating accesses to different versions of a memory element. The system supports a head thread that executes program instructions and a speculative thread that executes program instructions in advance of the head thread. The head thread accesses a primary version of the memory element, and the speculative thread accesses a space-time dimensioned version of the memory element. During a reference to the memory element by the head thread, the system accesses the primary version of the memory element. During a reference to the memory element by the speculative thread, the speculative thread accesses a pointer associated with the primary version of the memory element, and accesses a version of the memory element through the pointer. Note that the pointer points to the space-time dimensioned version of the memory element if the space-time dimensioned version of the memory element exists. In one embodiment of the present invention, the pointer points to the primary version of the memory element if the space-time dimensioned version of the memory element does not exist.

摘要翻译： 本发明的一个实施例提供一种通过促进对存储器元件的不同版本的访问来支持空间和时间维度程序执行的系统。 该系统支持执行程序指令的头部线程和在头部线程之前执行程序指令的推测线程。 头线程访问存储器元件的主要版本，并且推测线程访问存储器元件的时空维度版本。 在通过头部线程引用存储器元件期间，系统访问存储器元件的主要版本。 在通过推测线程对存储器元件的引用期间，推测线程访问与存储器元件的主版本相关联的指针，并且通过指针访问存储器元件的版本。 请注意，如果内存元素的时空维度版本存在，则指针指向内存元素的时空维度版本。 在本发明的一个实施例中，如果存储元件的时空尺寸版本不存在，则指针指向存储元件的主版本。

公开(公告)号：US06353881B1

公开(公告)日：2002-03-05

申请号：US09313229

申请日：1999-05-17

申请人： Shailender Chaudhry ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Marc Tremblay

IPC分类号： G06F952

CPC分类号： G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863

摘要： A system is provided that facilitates space and time dimensional execution of computer programs through selective versioning of memory elements located in a system heap. The system includes a head thread that executes program instructions and a speculative thread that simultaneously executes program instructions in advance of the head thread with respect to the time dimension of sequential execution of the program. The collapsing of the time dimensions is facilitated by expanding the heap into two space-time dimensions, a primary dimension (dimension zero), in which the head thread operates, and a space-time dimension (dimension one), in which the speculative thread operates. In general, each dimension contains its own version of an object and objects created by the thread operating in the dimension. The head thread generally accesses a primary version of a memory element and the speculative thread generally accesses a corresponding space-time dimensioned version of the memory element. During a write by the head thread, the system performs the write to all dimensions of the memory element. Note that if the dimensions are collapsed at this address a single update will update all time dimensions. It also checks status information associated with the memory element to determine if the memory element has been read by the speculative thread. If so, the system causes the speculative thread to roll back so that the speculative thread can read a result of the write operation.

摘要翻译： 提供了一种系统，其通过对位于系统堆中的存储器元件进行选择性版本化来促进计算机程序的空间和时间尺寸的执行。 该系统包括执行程序指令的头螺纹和相对于程序的顺序执行的时间维度在头部线程之前同时执行程序指令的推测线程。 通过将堆扩展到两个时空维度（头线程操作的主维度（维度零））和空时维度（维度一）来促进时间维度的崩溃，其中推测线程 操作。 通常，每个维度都包含自己的一个对象的版本，以及由维度中的线程创建的对象。 头部线程通常访问存储器元件的主要版本，并且推测线程通常访问存储器元件的对应的时空维度版本。 在头部线程的写入期间，系统对存储器元件的所有维进行写入。 请注意，如果维度在此地址中折叠，则单个更新将更新所有时间维。 它还检查与存储器元件相关联的状态信息以确定存储器元件是否已被推测性线程读取。 如果是这样，系统会使推测线程回滚，以便推测线程可以读取写入操作的结果。

公开(公告)号：US09256438B2

公开(公告)日：2016-02-09

申请号：US12354206

申请日：2009-01-15

申请人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Paul Caprioli ,  Marc Tremblay

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3857 ,  G06F9/30123 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3867

摘要： A computer processor pipeline has both an architectural register file and a working register file. The lifetime of an entry in the working register file is determined by a predetermined number of instructions passing through a specified stage in the pipeline after the location in the working register file is allocated for an instruction. The size of the working register file is selected based upon performance characteristics. A working register file creditor indicator is coupled to the front end pipeline portion and to the back end pipeline portion. The working register file credit indicator is monitored to prevent a working register file overflow. When the a location in the architectural register file is read early, the location is monitored to determine whether the location is written to prior to issuance of the instruction associated with the early read.

摘要翻译： 计算机处理器管道具有架构寄存器文件和工作寄存器文件。 在工作寄存器文件中的位置被分配给指令之后，在工作寄存器文件中的条目的寿命由通过流水线中的指定级的预定数量的指令确定。 基于性能特征选择工作寄存器文件的大小。 工作寄存器文件债权人指示器耦合到前端管道部分和后端管道部分。 监视工作寄存器文件信用指示符，以防止工作寄存器文件溢出。 当架构寄存器文件中的一个位置被提前读取时，监视该位置以确定在发出与早期读取相关联的指令之前是否写入位置。

公开(公告)号：US08219831B2

公开(公告)日：2012-07-10

申请号：US12361422

申请日：2009-01-28

申请人： Shailender Chaudhry ,  Quinn A. Jacobson ,  Marc Tremblay

发明人： Shailender Chaudhry ,  Quinn A. Jacobson ,  Marc Tremblay

IPC分类号： G06F1/32 ,  G06F9/30

CPC分类号： G06F9/3867 ,  G06F1/206 ,  G06F1/3203 ,  G06F9/3869 ,  Y02D10/16

摘要： A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages.

摘要翻译： 处理器包括提供节流功率输出信号的装置。 节流电源输出信号用于确定何时逻辑地调节处理器消耗的功率。 处理器中的至少一个核心包括具有解码管道的管线; 以及耦合到所述设备以接收所述输出信号并且耦合到所述解码管的逻辑功率节流单元。 在接收到满足预定标准的功率节流输出信号的逻辑功率节流单元之后，逻辑功率节流单元使得解码管减少在每个处理器周期解码的平均指令数，而不会物理地改变处理器周期或任何处理器供电电压。