公开(公告)号：US06335251B1

公开(公告)日：2002-01-01

申请号：US09824215

申请日：2001-04-03

申请人： Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Tomohiro Saito

发明人： Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Tomohiro Saito

IPC分类号： H01L21336

摘要： A semiconductor apparatus on which a MOS transistor having an elevated source and drain structure is formed is arranged to have a gate electrode which is formed on the surface of a silicon substrate through an insulating film. An elevated source film and an elevated drain film each having at least a surface portion constituted by a metal silicide film, being conductive and elevated over the surface of the silicon substrate are formed on a source region and a drain region on the surface of the silicon substrate. Thus, a MOS transistor having a structure in which the surfaces of the source region and the drain region are elevated over the surface of the silicon substrate is formed. A first gate-side-wall insulating film is formed on the side wall of the gate electrode of the MOS transistor and having a bottom surface formed apart from the surface of the silicon substrate. A second gate-side-wall insulating film is formed between the first gate-side-wall insulating film and the gate electrode and on the bottom surface of the first gate-side-wall insulating film. The portion formed on the bottom surface exists in an inner bottom surface portion of the bottom surface of the first gate-sidewall insulating film adjacent to the gate electrode. The elevated source film and the elevated drain film are free from any facet in portions made contact with the first gate-side-wall insulating film.

公开(公告)号：US5406115A

公开(公告)日：1995-04-11

申请号：US52919

申请日：1993-04-27

申请人： Takeo Maeda ,  Hiroshi Gojohbori ,  Yoshitaka Tsunashima

发明人： Takeo Maeda ,  Hiroshi Gojohbori ,  Yoshitaka Tsunashima

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L27/06 ,  H01L29/10 ,  H01L29/732 ,  H01L29/72 ,  H01L27/02

CPC分类号： H01L29/7322 ,  H01L27/0623 ,  H01L29/1004

摘要： A semiconductor device of this invention includes an N-type semiconductor region functioning as a collector of a bipolar transistor, a silicon dioxide film doped with boron and formed in contact with the surface of the N-type semiconductor region, a P-type semiconductor region formed in contact with the silicon dioxide film doped with boron in the N-type semiconductor region and functioning as a base of the bipolar transistor, and an N-type semiconductor region formed in the P-type semiconductor region and functioning as an emitter of the bipolar transistor.

摘要翻译： 本发明的半导体器件包括用作双极晶体管的集电极的N型半导体区域，掺杂有硼并与N型半导体区域的表面接触形成的二氧化硅膜，P型半导体区域 形成为与N型半导体区域中掺杂有硼的二氧化硅膜接触并用作双极晶体管的基极，并且形成在P型半导体区域中并用作发光体的N型半导体区域 双极晶体管。

公开(公告)号：US5324686A

公开(公告)日：1994-06-28

申请号：US959457

申请日：1992-10-09

申请人： Yoshitaka Tsunashima

发明人： Yoshitaka Tsunashima

IPC分类号： H01L21/22 ,  H01L21/225 ,  H01L21/318 ,  H01L21/334 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66181 ,  H01L21/2225 ,  H01L21/2255 ,  H01L21/3185 ,  H01L29/6659 ,  H01L29/78

摘要： A method of manufacturing a semiconductor device, which comprises the steps of forming a solid phase diffusion source containing a conductive impurity on a surface of a semiconductor substrate, said impurity serving to enable said semiconductor substrate to exhibit a p-type or n-type conductivity, allowing said solid phase diffusion source to contain a diffusion control substance serving to reduce or oxidize said conductive impurity upon heating so as to change the diffusion coefficient of the conductive impurity contained in the solid phase diffusion source, and thermally diffusing the conductive impurity from the solid phase diffusion source into the semiconductor substrate.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在半导体衬底的表面上形成含有导电杂质的固相扩散源，所述杂质用于使得所述半导体衬底能够显示p型或n型导电性 允许所述固相扩散源包含用于在加热时减少或氧化所述导电杂质的扩散控制物质，以便改变固相扩散源中所含的导电杂质的扩散系数，并将导电杂质从 固相扩散源进入半导体衬底。

公开(公告)号：US4791074A

公开(公告)日：1988-12-13

申请号：US073473

申请日：1987-07-15

申请人： Yoshitaka Tsunashima ,  Keisaku Yamada ,  Takako Kashio

发明人： Yoshitaka Tsunashima ,  Keisaku Yamada ,  Takako Kashio

IPC分类号： H01L21/225 ,  H01L21/385

CPC分类号： H01L21/2254 ,  Y10S148/158

摘要： According to the present invention, a method of manufacturing a semiconductor apparatus is provided which comprises the steps of (a) depositing a boron layer on a silicon substrate, and (b) thermally diffusing boron from said boron layer into said silicon substrate. The present invention, which is characteristically based on the solid phase diffusion process, enables even a thin layer to be deposited. Further, unlike the ion implantation process, the present invention enables an impurity to be uniformly diffused even into an inclined plane. Unlike the case where boron-containing glass is used as a diffusion source, the invention enables a sufficient amount of boron to be diffused even at a temperature lower than 1000.degree. C.

摘要翻译： 根据本发明，提供一种制造半导体器件的方法，其包括以下步骤：（a）在硅衬底上沉积硼层，和（b）将硼从所述硼层热扩散到所述硅衬底中。 本发明特征在于基于固相扩散工艺，甚至能够沉积薄层。 此外，与离子注入工艺不同，本发明使得杂质均匀均匀地扩散到倾斜平面中。 与使用含硼玻璃作为扩散源的情况不同，本发明即使在低于1000℃的温度下也能够使足量的硼扩散。

公开(公告)号：US07879658B2

公开(公告)日：2011-02-01

申请号：US12040224

申请日：2008-02-29

申请人： Yoshio Ozawa ,  Ichiro Mizushima ,  Takashi Suzuki ,  Hirokazu Ishida ,  Yoshitaka Tsunashima

发明人： Yoshio Ozawa ,  Ichiro Mizushima ,  Takashi Suzuki ,  Hirokazu Ishida ,  Yoshitaka Tsunashima

IPC分类号： H01L21/00 ,  H01L29/04

CPC分类号： H01L29/788 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/04

摘要： A semiconductor device includes a silicon crystal layer on an insulating layer, the silicon crystal layer containing a crystal lattice mismatch plane, a memory cell array portion on the silicon crystal layer, the memory cell array portion including memory strings, each of the memory strings including nonvolatile memory cell transistors connected in series in a first direction, the memory strings being arranged in a second direction orthogonal to the first direction, the crystal lattice mismatch plane crossing the silicon crystal along the second direction without passing under gates of the nonvolatile memory cell transistors as viewed from a top of the silicon crystal layer, or crossing the silicon crystal along the first direction with passing under gates of the nonvolatile memory cell transistors as viewed from the top of the silicon crystal layer.

摘要翻译： 半导体器件包括绝缘层上的硅晶体层，含有晶格失配平面的硅晶体层，硅晶体层上的存储单元阵列部分，存储单元阵列部分包括存储器串，每个存储器串包括 所述非易失性存储单元晶体管沿第一方向串联连接，所述存储器串沿与所述第一方向正交的第二方向布置，所述晶格失配面沿着所述第二方向与所述硅晶体交叉，而不通过所述非易失性存储单元晶体管的栅极 从硅晶体层的顶部观察，或者从硅晶体层的顶部观察时沿着非易失性存储单元晶体管的栅极通过硅晶体沿第一方向。

公开(公告)号：US07544593B2

公开(公告)日：2009-06-09

申请号：US11999958

申请日：2007-12-07

申请人： Yoshitaka Tsunashima ,  Seiji Ihumiya ,  Yasumasa Suizu ,  Yoshio Ozawa ,  Kiyotaka Miyano ,  Masayuki Tanaka

发明人： Yoshitaka Tsunashima ,  Seiji Ihumiya ,  Yasumasa Suizu ,  Yoshio Ozawa ,  Kiyotaka Miyano ,  Masayuki Tanaka

IPC分类号： H01L21/28 ,  H01L21/44

CPC分类号： H01L21/82345 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/31604 ,  H01L21/823462 ,  H01L21/823475 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656

摘要： Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.

摘要翻译： 权利要求和公开的是一种半导体器件，包括具有在包含金属，硅和氧的金属硅酸盐的化合物中含有氮或氟的栅极绝缘膜结构的晶体管，具有非晶态金属氧化物层叠结构的栅极绝缘膜结构 膜和金属硅酸盐膜，或具有包括第一金属元素的氧化物膜的第一栅极绝缘膜和包括第二金属元素的金属硅酸盐膜的第二栅极绝缘膜的栅极绝缘膜结构。

公开(公告)号：US20090121279A1

公开(公告)日：2009-05-14

申请号：US12249354

申请日：2008-10-10

申请人： Hirokazu Ishida ,  Takashi Suzuki ,  Yoshio Ozawa ,  Ichiro Mizushima ,  Yoshitaka Tsunashima

发明人： Hirokazu Ishida ,  Takashi Suzuki ,  Yoshio Ozawa ,  Ichiro Mizushima ,  Yoshitaka Tsunashima

IPC分类号： H01L21/20 ,  H01L29/786

CPC分类号： H01L27/11521 ,  H01L21/84 ,  H01L27/11524 ,  H01L27/1203

摘要： A semiconductor device includes a single crystal silicon substrate an insulating layer partially formed on the single crystal silicon substrate, a single crystal silicon layer formed on the single crystal silicon substrate and the insulating layer, and containing a defect layer resulting from an excessive group IV element, and a plurality of first gate structures for memory cells, each including a first gate insulating film formed on the single crystal silicon layer, a charge storage layer formed on the first gate insulating film, a second gate insulating film formed on the charge storage layer, and a control gate electrode formed on the second gate insulating film.

摘要翻译： 半导体器件包括单晶硅衬底，部分地形成在单晶硅衬底上的绝缘层，形成在单晶硅衬底上的单晶硅层和绝缘层，并且包含由过量IV族元素产生的缺陷层 以及多个用于存储单元的第一栅极结构，每个包括形成在单晶硅层上的第一栅极绝缘膜，形成在第一栅极绝缘膜上的电荷存储层，形成在电荷存储层上的第二栅极绝缘膜 以及形成在第二栅极绝缘膜上的控制栅电极。

公开(公告)号：US07425480B2

公开(公告)日：2008-09-16

申请号：US11790064

申请日：2007-04-23

申请人： Yoshio Ozawa ,  Yasumasa Suizu ,  Yoshitaka Tsunashima

发明人： Yoshio Ozawa ,  Yasumasa Suizu ,  Yoshitaka Tsunashima

IPC分类号： H01L21/84

CPC分类号： H01L29/7881 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02233 ,  H01L21/02271 ,  H01L21/28044 ,  H01L21/28202 ,  H01L21/28247 ,  H01L21/28273 ,  H01L21/3144 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833 ,  Y10S438/911 ,  Y10S438/942 ,  Y10S438/947 ,  Y10S438/966

摘要： A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode is formed on the gate electrode insulating film, and an oxidation process using ozone is performed to sufficiently round the shape of the lower edge of the gate electrode.

摘要翻译： 一种制造包含用作栅极绝缘膜并含有氮的氧化硅膜和用作栅电极并含有掺杂剂的多晶硅膜的MOS晶体管的方法，其布置使得栅电极形成在栅电极绝缘膜上 ，并且进行使用臭氧的氧化处理以充分地绕着栅电极的下边缘的形状。

公开(公告)号：US07312138B2

公开(公告)日：2007-12-25

申请号：US11790033

申请日：2007-04-23

申请人： Yoshio Ozawa ,  Yasumasa Suizu ,  Yoshitaka Tsunashima

发明人： Yoshio Ozawa ,  Yasumasa Suizu ,  Yoshitaka Tsunashima

IPC分类号： H01L21/3205

CPC分类号： H01L29/7881 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02233 ,  H01L21/02271 ,  H01L21/28044 ,  H01L21/28202 ,  H01L21/28247 ,  H01L21/28273 ,  H01L21/3144 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833 ,  Y10S438/911 ,  Y10S438/942 ,  Y10S438/947 ,  Y10S438/966

摘要： A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode is formed on the gate electrode insulating film, and an oxidation process using ozone is performed to sufficiently round the shape of the lower edge of the gate electrode.

公开(公告)号：US20070218606A1

公开(公告)日：2007-09-20

申请号：US11790064

申请日：2007-04-23

申请人： Yoshio Ozawa ,  Yasumasa Suizu ,  Yoshitaka Tsunashima

发明人： Yoshio Ozawa ,  Yasumasa Suizu ,  Yoshitaka Tsunashima

IPC分类号： H01L21/84

CPC分类号： H01L29/7881 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02233 ,  H01L21/02271 ,  H01L21/28044 ,  H01L21/28202 ,  H01L21/28247 ,  H01L21/28273 ,  H01L21/3144 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833 ,  Y10S438/911 ,  Y10S438/942 ,  Y10S438/947 ,  Y10S438/966

摘要： A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode is formed on the gate electrode insulating film, and an oxidation process using ozone is performed to sufficiently round the shape of the lower edge of the gate electrode.

摘要翻译： 一种制造包含用作栅极绝缘膜并含有氮的氧化硅膜和用作栅电极并含有掺杂剂的多晶硅膜的MOS晶体管的方法，其布置使得栅电极形成在栅电极绝缘膜上 ，并且进行使用臭氧的氧化处理以充分地绕着栅电极的下边缘的形状。