-
公开(公告)号：US07173877B2
公开(公告)日：2007-02-06
申请号：US10955177
申请日：2004-09-30
IPC分类号： G11C8/00
CPC分类号： G11C5/04 , G11C5/063 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory device, a memory controller to control operation of the memory device, a first clock line which extends from a write clock output of the memory controller to a clock port of the memory device to provide a clock signal to the memory device, and a second clock line which extends from the clock port of the memory device to a read clock input of the memory controller to forward the clock signal applied to the clock port of the memory device back to a read clock input of the memory controller. The memory device may further comprise a synchronization circuit adapted to receive the clock signal from the memory controller and to, provide an output data synchronized to the forwarded clock signal.
摘要翻译： 本发明涉及一种具有两条时钟线的存储器件的存储器系统。 本发明的一个实施例提供了一种存储器系统，其包括至少一个存储器件，用于控制存储器件的操作的存储器控制器，从存储器控制器的写时钟输出延伸到存储器的时钟端口的第一时钟线 向存储器件提供时钟信号的第二时钟线，以及从存储器件的时钟端口延伸到存储器控制器的读时钟输入端的第二时钟线，以将施加到存储器件的时钟端口的时钟信号转发回 到存储器控制器的读时钟输入。 存储器件还可以包括同步电路，其适于从存储器控制器接收时钟信号，并提供与转发的时钟信号同步的输出数据。
-
公开(公告)号：US20070025131A1
公开(公告)日：2007-02-01
申请号：US11192335
申请日：2005-07-29
IPC分类号： G11C5/06
摘要： The present invention includes a semiconductor memory modules and semiconductor memory systems using the same. The modules divide a conventional DIMM into a series of separate, smaller memory modules. Each memory module includes at least one semiconductor memory chip arranged on a substrate; CAwD signal input lines arranged on the substrate in a first predetermined line number and connecting one of the semiconductor memory chips to CAwD input signal pins on the substrate; and rD signal output lines arranged on the substrate in a second predetermined line number and connecting the one or a last semiconductor memory to a second number of rD output signal pins of the substrate. In a semiconductor memory system including the semiconductor memory modules, each memory module is separately connected to a memory controller by the CAwD signal input linesand the rD signal output lines in a respective point-to-point fashion.
摘要翻译： 本发明包括半导体存储器模块和使用其的半导体存储器系统。 这些模块将常规DIMM分成一系列独立的较小内存模块。 每个存储器模块包括布置在衬底上的至少一个半导体存储器芯片; CAwD信号输入线，以第一预定行号排列在基板上，并将半导体存储器芯片之一连接到基板上的CAwD输入信号引脚; 和rD信号输出线，以第二预定行号排列在基板上，并将一个或最后一个半导体存储器连接到基板的第二数量的rD输出信号引脚。 在包括半导体存储器模块的半导体存储器系统中，每个存储器模块通过CAwD信号输入线和rD信号输出线分别以点对点的方式连接到存储器控制器。
-
公开(公告)号：US20060265543A1
公开(公告)日：2006-11-23
申请号：US11130412
申请日：2005-05-17
申请人： Peter Oeschay , Hermann Ruckerbauer
发明人： Peter Oeschay , Hermann Ruckerbauer
IPC分类号： G06F12/06
CPC分类号： G06F12/0676 , G11C5/066 , G11C8/12
摘要： A method for setting an address of a rank in a memory module having a number of memory chips distributed along a byte lane includes setting the first memory chip of the byte lane to have a first rank address, generating a second rank address therein from the first rank address, and driving the second rank address to a second one of the memory chips. Alternatively, the first rank address may be driven to the second memory chip, and then, a second rank address is generated in that second memory chip. Further, the second memory chip is set to have the second rank address in response to the driving the second/first rank address. A power-up sequence after voltage supply, or command signals sent via a serial management bus or the command address bus can be used to initiate the setting of ranks. The rank addresses are re-driven to adjacent memory chips by DQ-lines along a byte lane.
摘要翻译： 一种用于设置具有沿着字节通道分配的存储器芯片数量的存储器模块中的等级地址的方法，包括：将字节通道的第一存储器芯片设置为具有第一等级地址，从第一级地址生成第二等级地址 并且将第二等级地址驱动到第二个存储器芯片。 或者，第一等级地址可以被驱动到第二存储器芯片，然后在该第二存储器芯片中产生第二等级地址。 此外，响应于驱动第二/第一等级地址，将第二存储器芯片设置为具有第二等级地址。 通过串行管理总线或命令地址总线发送电源后的上电序列，或命令信号可以用来启动等级的设置。 等级地址沿着字节通道被DQ线重新驱动到相邻的存储器芯片。
-
公开(公告)号：US20060248260A1
公开(公告)日：2006-11-02
申请号：US11392217
申请日：2006-03-29
申请人： Maksim Kuzmenka , Simon Muff , Hermann Ruckerbauer
发明人： Maksim Kuzmenka , Simon Muff , Hermann Ruckerbauer
IPC分类号： G06F12/02
CPC分类号： H03K19/018514 , H03K19/0175 , H03K19/01812
摘要： A circuit system includes a means for controlling a first and a second memory unit by means of a differential control signal. The differential control signal includes a first control signal and a second control signal, which is inverted to the first control signal. Further, the circuit system comprises a differential control signal line, which includes a first signal line for routing the first control signal and a second signal line for routing the second control signal. The first switching unit is connected via the first signal line and the second circuit unit is connected via the second signal line to the means for controlling.
摘要翻译： 电路系统包括用于通过差分控制信号控制第一和第二存储器单元的装置。 差分控制信号包括第一控制信号和第二控制信号，其被反转到第一控制信号。 此外，电路系统包括差分控制信号线，其包括用于路由第一控制信号的第一信号线和用于路由第二控制信号的第二信号线。 第一开关单元经由第一信号线连接，第二电路单元经由第二信号线连接到控制装置。
-
公开(公告)号：US07061784B2
公开(公告)日：2006-06-13
申请号：US10886814
申请日：2004-07-08
IPC分类号： G11C5/06
CPC分类号： G11C11/4093 , G11C5/063 , G11C7/10
摘要： The invention relates to a semiconductor memory module having at least one memory chip and a buffer chip, which drives clock, address and command signals to the memory chip and drives data signals to, and receives them from, the memory chip via a module-internal clock, address, command and data bus. The buffer chip forms an interface to an external memory main bus. The data bus lines and/or the clock, command and address bus lines are respectively connected to the buffer chip at their two ends and are capable of being driven by the buffer chip from these two ends. Control means are being provided and set up in such a manner that they respectively match the directions of propagation of the data signals and of the clock, command and address signals on the corresponding bus lines during writing and reading.
摘要翻译： 本发明涉及一种具有至少一个存储器芯片和缓冲芯片的半导体存储器模块，其将时钟，地址和命令信号驱动到存储器芯片，并且经由模块内部驱动数据信号并从存储器芯片接收它们 时钟，地址，命令和数据总线。 缓冲芯片形成与外部存储器主总线的接口。 数据总线和/或时钟，命令和地址总线分别在两端分别连接到缓冲芯片，并且能够被这两端的缓冲芯片驱动。 正在提供和设置控制装置，使得它们在写入和读取期间它们分别匹配数据信号的传播方向以及相应总线上的时钟，命令和地址信号。
-
公开(公告)号：US20060112239A1
公开(公告)日：2006-05-25
申请号：US10993165
申请日：2004-11-19
申请人： Hermann Ruckerbauer
发明人： Hermann Ruckerbauer
IPC分类号： G06F13/00
CPC分类号： G06F13/4243
摘要： A memory device for use in a memory module and method for operating the memory device are provided. In one embodiment, the memory device comprises a memory array, a memory access logic for controlling access to the memory array depending on a command data, a command interface for establishing a point to point interconnect to a memory controller and comprising a first and a second command port for receiving first and second command signals indicating the command data and, a repeater unit for receiving the first command signal via the first command port and for forwarding the first command signal to a forwarding port.
摘要翻译： 提供了用于存储器模块的存储器件和用于操作存储器件的方法。 在一个实施例中，存储器设备包括存储器阵列，用于根据命令数据控制对存储器阵列的访问的存储器访问逻辑，用于建立与存储器控制器的点对点互连的命令接口，并且包括第一和第二 命令端口，用于接收指示命令数据的第一和第二命令信号;以及中继器单元，用于经由第一命令端口接收第一命令信号，并将第一命令信号转发到转发端口。
-
67.发明授权Semiconductor memory system and method for the transfer of write and read data signals in a semiconductor memory system 有权半导体存储器系统和用于在半导体存储器系统中传送写和读数据信号的方法公开(公告)号：US07050340B1
公开(公告)日：2006-05-23
申请号：US10986767
申请日：2004-11-15
IPC分类号： G11C7/00
CPC分类号： G11C7/1045 , G11C5/04 , G11C7/1018
摘要： A semiconductor memory system for the transfer of write and read data signals among interface circuits includes at least one memory device, a memory controller unit and, optionally, a register unit of a semiconductor memory system, wherein the data signals are each transferred in signal bursts of a specific burst length. The system is characterized in that a number of additional bits extending the burst length are transferred together with at least every nth signal burst.
摘要翻译： 用于在接口电路之间传送写入和读取数据信号的半导体存储器系统包括至少一个存储器件，存储器控制器单元和可选地半导体存储器系统的寄存器单元，其中数据信号各自以信号脉冲串 具体的突发长度。 该系统的特征在于，延伸突发长度的多个附加位与至少每个第n个信号脉冲串一起传送。
-
公开(公告)号：US20060092715A1
公开(公告)日：2006-05-04
申请号：US11099222
申请日：2005-04-05
IPC分类号： G11C7/10
CPC分类号： G11C7/1084 , G11C7/1078 , G11C7/1093 , G11C7/14
摘要： A circuit exhibits a signal input, means for determining a reference level on the basis of properties of a signal received at the signal input. In addition, the circuit further exhibits means for evaluating the signal on the basis of the reference level.
摘要翻译： 电路呈现信号输入，用于基于在信号输入处接收的信号的特性来确定参考电平的装置。 此外，电路还具有用于基于参考电平来评估信号的装置。
-
69.发明授权公开(公告)号：US06840808B2
公开(公告)日：2005-01-11
申请号：US10610241
申请日：2003-06-30
CPC分类号： H01R12/52 , H01R12/716
摘要： A connector is described for fixing a plurality of switching assemblies on a substrate. The connector is also for making contact with the plurality of switching assemblies, which have compatible interfaces. The connector has a plurality of receptacle devices with contact elements and internal contact connections between corresponding contact elements, as a result of which, the length of the connections between the switching assemblies is reduced, signal propagation times are shortened and a higher clock rate for operating the switching assemblies is made possible.
摘要翻译： 描述了用于将多个开关组件固定在基板上的连接器。 连接器还用于与具有兼容接口的多个开关组件接触。 连接器具有多个具有接触元件的插座装置和相应的接触元件之间的内部接触连接，其结果是，开关组件之间的连接长度减小，信号传播时间缩短，操作时钟频率更高 开关组件成为可能。
-
公开(公告)号：US06819625B2
公开(公告)日：2004-11-16
申请号：US10266353
申请日：2002-10-07
申请人： Hermann Ruckerbauer , Andre Schäfer
发明人： Hermann Ruckerbauer , Andre Schäfer
IPC分类号： G11C700
摘要： A memory device has a memory module, a controller, a data bus for connecting the controller and the memory module, a read clock generator, and a read clock bus for connecting the read clock generator, the memory module, and the Controller. The data bus read data from the memory module or writes data into the memory module. The read clock generator is disposed in the memory module, so that the data bus and the read clock bus are substantially symmetric, and generate a read clock for transferring data from the memory module to the controller. The data bus and the read clock bus are configured with respect to each other such that substantially no time delay between read data on the data bus and the read clock on the read clock bus exists at the controller.
摘要翻译： 存储器件具有存储器模块，控制器，用于连接控制器和存储器模块的数据总线，读时钟发生器和用于连接读时钟发生器，存储器模块和控制器的读时钟总线。 数据总线从存储器模块读取数据或将数据写入存储器模块。 读时钟发生器设置在存储器模块中，使得数据总线和读时钟总线基本对称，并且生成用于将数据从存储器模块传送到控制器的读时钟。 数据总线和读时钟总线相对于彼此配置，使得在控制器上存在数据总线上的读数据和读时钟总线上的读时钟之间基本上没有时间延迟。
-
-
-
-
-
-
-
-
-
搜索结果
135 条记录 (耗时 0.027 秒)
