公开(公告)号：US20050048715A1

公开(公告)日：2005-03-03

申请号：US10651392

申请日：2003-08-29

申请人： Thomas Rupp ,  Stephan Kudelka ,  Alexander Michaelis ,  Carl Radens

发明人： Thomas Rupp ,  Stephan Kudelka ,  Alexander Michaelis ,  Carl Radens

IPC分类号： H01L21/334 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/108 ,  H01L29/94

CPC分类号： H01L29/945 ,  H01L27/10864 ,  H01L27/1087 ,  H01L29/66181

摘要： A trench capacitor having a conductive pillar in a central region of a trench. A first plate of the capacitor includes the substrate in the lower portion of the trench and the conductive pillar. The capacitor dielectric is disposed over the conductive pillar and the sidewalls of the trench lower portion. A second plate of the capacitor is a conductive material disposed over the dielectric material. The conductive pillar increases the surface area of the capacitor plates, increasing the capacitance of the capacitor. A top portion of the conductive pillar may be hollow, further increasing the surface area of the capacitor plates.

摘要翻译： 一种在沟槽的中心区域具有导电柱的沟槽式电容器。 电容器的第一板包括沟槽下部的基片和导电柱。 电容器电介质设置在导电柱和沟槽下部的侧壁之上。 电容器的第二板是设置在电介质材料上的导电材料。 导电柱增加电容器板的表面积，增加电容器的电容。 导电柱的顶部可以是中空的，进一步增加电容器板的表面积。

公开(公告)号：US06740555B1

公开(公告)日：2004-05-25

申请号：US09408248

申请日：1999-09-29

申请人： Helmut Horst Tews ,  Alexander Michaelis ,  Stephan Kudelka ,  Uwe Schroeder ,  Raj Jammy ,  Ulrike Gruening

发明人： Helmut Horst Tews ,  Alexander Michaelis ,  Stephan Kudelka ,  Uwe Schroeder ,  Raj Jammy ,  Ulrike Gruening

IPC分类号： H01L218242

CPC分类号： H01L21/28202 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/2822 ,  H01L21/3144 ,  H01L21/31658 ,  H01L27/10864 ,  H01L29/045 ,  H01L29/42368 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/7827 ,  Y10S257/905

摘要： A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of axis. A trench is formed in a surface of the silicon body, such trench having sidewalls disposed in different crystallographic planes, one of such planes being the crystallographic plane and another one of such planes being the plane. A substantially uniform layer of silicon nitride is formed on the sidewalls. The trench, with the substantially uniform layer of silicon nitride, is subjected to a silicon oxidation environment with sidewalls in the plane being oxidized at a higher rate than sidewalls in the plane producing silicon dioxide on the silicon nitride layer having thickness over the plane greater than over the plane. The silicon dioxide is subjected to an etch to selectively remove silicon dioxide while leaving substantially un-etched silicon nitride to thereby remove portions of the silicon dioxide over the plane and to thereby expose underlying portions of the silicon nitride material while leaving portions of the silicon dioxide over the plane on underlying portions of the silicon nitride material. Exposed portions of the silicon nitride material are selectively removed to expose underlying portions of the sidewalls of the trench disposed in the plane while leaving substantially un-etched portions of the silicon nitride material disposed on sidewalls of the trench disposed in the plane. The structure is then subjected to an silicon oxidation environment to produce the substantially uniform silicon dioxide layer on the sidewalls of the trench.

摘要翻译： 一种用于在独立于轴的硅体上形成基本上均匀的厚的，热生长的二氧化硅材料的方法。 沟槽形成在硅体的表面中，这种沟槽具有设置在不同结晶平面内的侧壁，其中一个这样的平面是<100>结晶平面，另外一个这样的平面是<110>平面。 在侧壁上形成基本均匀的氮化硅层。 具有基本上均匀的氮化硅层的沟槽经受硅氧化环境，其中<110>面中的侧壁以比在100平面中的侧壁更高的速率被氧化，在氮化硅层上产生二氧化硅， 厚度大于<100>平面上的厚度。 对二氧化硅进行蚀刻以选择性地去除二氧化硅，同时留下基本未蚀刻的氮化硅，从而在<100>平面上除去二氧化硅的一部分，从而暴露氮化硅材料的下面部分，同时留下部分 在氮化硅材料的下面部分上的<110>面上的二氧化硅。 选择性地去除氮化硅材料的暴露部分以暴露设置在<100>平面中的沟槽的侧壁的下面部分，同时留下设置在设置在<110>平面中的沟槽的侧壁上的氮化硅材料的基本上未蚀刻的部分 >飞机。 然后将该结构进行硅氧化环境以在沟槽的侧壁上产生基本均匀的二氧化硅层。

公开(公告)号：US06670235B1

公开(公告)日：2003-12-30

申请号：US09939554

申请日：2001-08-28

申请人： Helmut Horst Tews ,  Stephan Kudelka ,  Oliver Genz

发明人： Helmut Horst Tews ,  Stephan Kudelka ,  Oliver Genz

IPC分类号： H01L218242

CPC分类号： H01L27/10861 ,  H01L27/1087

摘要： In a method of forming a DRAM cell in a semiconductor substrate, the improvement of maintaining a substantially full trench opening during trench processing comprising: a) forming a pad nitride on the surface of the substrate and reactive ion etching (RIE) a trench vertically to a first depth; b) depositing a nitride layer in the trench; c) filling the trench with a poly silicon fill; d) recess etching the fill to the collar depth; e) oxidizing to transform the exposed nitride layer into a nitrided oxide collar or depositing an oxide on the layer of nitride; f) reactive ion etching to open the bottom oxide; g) stripping the poly fill trench, and performing a nitride etch selective to oxide; h) expanding the trench horizontally by etching lower trench sidewalls and bottom while masking the upper sidewalls; i) forming a buried plate at the bottom of the trench sidewalls; j) forming the node dielectric in the deep trench to grow a collar oxide that consists of a nitrided oxide and a layer of node nitride; k) filling the trench with a poly fill; l) recess etching the poly fill approximately to the collar bottom; m) depositing a collar oxide; n) reactive ion etching to open the bottom; o) filling the trench with a poly fill; and p) chemically mechanically polishing the semiconductor substrate.

摘要翻译： 在半导体衬底中形成DRAM单元的方法中，在沟槽处理期间保持基本上完整的沟槽开口的改进包括：a）在衬底的表面上形成衬垫氮化物，并且反应离子蚀刻（RIE）垂直于 第一深度; b）在沟槽中沉积氮化物层; c）用多晶硅填充物填充沟槽; d）将填充物凹陷蚀刻到套环深度; e）氧化以将暴露的氮化物层转变成氮化的氧化物环或在氮化物层上沉积氧化物; f）反应离子蚀刻以打开底部氧化物; g）剥离多晶填充沟槽，并对氧化物进行选择性的氮化物蚀刻; h）通过在掩蔽上侧壁的同时蚀刻下沟槽侧壁和底部来水平地扩展沟槽; i）在沟槽侧壁的底部形成掩埋板; j）在深沟槽中形成节点电介质以生长由氮化氧化物和节点氮化物层组成的环状氧化物; k）用多孔填充物填充沟槽; l）凹槽将多孔填充物蚀刻到接近底部; m）沉积环氧化物; n）反应离子蚀刻打开底部; o）用多孔填充填充沟槽; 和p）化学机械抛光半导体衬底。

公开(公告)号：US06605838B1

公开(公告)日：2003-08-12

申请号：US10261219

申请日：2002-09-30

申请人： Jack A. Mandelman ,  Rama Divakaruni ,  Gerd Fehlauer ,  Stephan Kudelka ,  Uwe Schroeder ,  Helmut H. Tews

发明人： Jack A. Mandelman ,  Rama Divakaruni ,  Gerd Fehlauer ,  Stephan Kudelka ,  Uwe Schroeder ,  Helmut H. Tews

IPC分类号： H01L27108

CPC分类号： H01L27/10867 ,  H01L27/10841 ,  H01L27/10864 ,  H01L29/66181 ,  H01L29/945

摘要： A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 &mgr;m or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.

摘要翻译： 提供了沟槽电容器存储单元结构，其包括垂直轴环区域，其抑制存在于垂直MOSFET和下面的沟槽电容器之间的相邻垂直寄生晶体管的电流泄漏。 具有约0.50μm或更小的垂直长度的垂直环形隔离件包括部分在沟槽外部存在的第一部分和存在于沟槽内部的第二部分。 轴环氧化物的第一部分比所述第二部分氧化物厚，从而减少了寄生电流泄漏。

公开(公告)号：US06486024B1

公开(公告)日：2002-11-26

申请号：US09577102

申请日：2000-05-24

申请人： Helmut Horst Tews ,  Alexander Michaelis ,  Stephan Kudelka ,  Uwe Schroeder ,  Ulrike Gruening

发明人： Helmut Horst Tews ,  Alexander Michaelis ,  Stephan Kudelka ,  Uwe Schroeder ,  Ulrike Gruening

IPC分类号： H01L218242

CPC分类号： H01L27/10861

摘要： A method of using at least two insulative layers to form the isolation collar of a trench device, and the device formed therefrom. The first layer is preferably an oxide (e.g., silicon dioxide 116) formed on the trench substrate sidewalls, and is formed through a TEOS, LOCOS, or combined TEOS/LOCOS process. Preferably, both the TEOS process and the LOCOS process are used to form the first layer. The second layer is preferably a silicon nitride layer (114) formed on the oxide layer. The multiple layers function as an isolation collar stack for the trench. The dopant penetration barrier properties of the second layer permit the dielectric collar stack to be used as a self aligned mask for subsequent buried plate (120) doping.

摘要翻译： 一种使用至少两个绝缘层以形成沟槽器件的隔离套环的方法，以及由其形成的器件。 第一层优选是形成在沟槽衬底侧壁上的氧化物（例如，二氧化硅116），并且通过TEOS，LOCOS或组合的TEOS / LOCOS工艺形成。 优选地，TEOS工艺和LOCOS工艺都用于形成第一层。 第二层优选是形成在氧化物层上的氮化硅层（114）。 多层用作沟槽的隔离环叠层。 第二层的掺杂剂渗透阻挡性质允许电介质套管叠层用作后续掩埋板（120）掺杂的自对准掩模。

公开(公告)号：US06352893B1

公开(公告)日：2002-03-05

申请号：US09324927

申请日：1999-06-03

申请人： Alexander Michaelis ,  Stephan Kudelka ,  Jochen Beintner ,  Oliver Genz

发明人： Alexander Michaelis ,  Stephan Kudelka ,  Jochen Beintner ,  Oliver Genz

IPC分类号： H01L218242

CPC分类号： H01L21/02238 ,  C25D11/32 ,  H01L21/02258 ,  H01L21/31675 ,  H01L27/10861

摘要： A method for fabricating a semiconductor device, in accordance with the present invention, includes the steps of providing a semiconductor wafer having exposed p-doped silicon regions and placing the wafer in an electrochemical cell such that a solution including electrolytes interacts with the exposed p-doped silicon regions to form an oxide on the exposed p-doped silicon regions when a potential difference is provided between the wafer and the solution.

摘要翻译： 根据本发明的用于制造半导体器件的方法包括以下步骤：提供具有暴露的p掺杂硅区域的半导体晶片并将晶片放置在电化学电池中，使得包含电解质的溶液与暴露的p掺杂硅区域相互作用， 当在晶片和溶液之间提供电位差时，掺杂的硅区域在暴露的p掺杂的硅区域上形成氧化物。